# US 8,570,259 B2 · Scan method for liquid crystal display

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- Number: US 8,570,259 B2
- Document ID: US8570259B2
- Status: Granted
- Kind: B2
- Application number: 11/152,492
- Filed: 2005-06-14
- Published: 2006-08-17
- Granted: 2013-10-29
- Earliest claimed: 2005-02-17
- Assignees: Au Optronics Corporation
- Applicants: Huan-Hsin Li; Yao-Jen Hsieh; Chih-Sung Wang
- Inventors: Huan-Hsin Li; Yao-Jen Hsieh; Chih-Sung Wang
- Web page: https://patentgrep.com/patent/US8570259B2

## CPC

- G09G 3/3666: {with the matrix divided into sections}
- G09G 2310/0218: with collection of electrodes in groups for n-dimensional addressing
- G09G 2310/0221: with use of split matrices (G09G3/3644 and G09G3/3666 take precedence)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A scan method for use in a flat panel display comprising K groups of lines, comprising the following steps. First, K sequences S1 to SK are provided. A scan order is then determined according to the K sequences S1 to SK. Thereafter, the K groups of lines are synchronously scanned by the scan order. K is an integer not less than 2. Each group of lines comprises at least M lines.

## Claims

### Claim 1

A scan method for a flat panel display comprising Y lines divided into K groups, comprising:
providing K sequences S1 to SK;
determining an interlaced scan order by interlacing the K sequences S1 to SK; and
synchronously scanning the K groups of lines based on the interlaced scan order such that each group of lines is scanned K times per Y scan time slots and the each group of lines is scanned alternately, and any two lines in each group of lines are not scanned at the same time in one scan slot; wherein K is an integer not less than 2, wherein:
Si(x)=(x+Ni)(mod M), i=1 to K, x=1 to M;
Where Si(x) denotes the xth element in sequence Si.

### Claim 2 (depends on 1)

The scan method as claimed in claim 1, wherein:
each group of lines comprises at least M lines;
the step of providing K sequences S1 to SK comprises:
providing K shift values N1 to NK, wherein the shift values are not greater than M;
determining the sequences S1 to SK based on the shift values N1 to NK; and
the step of determining the interlaced scan order comprises sequentially selecting all the first elements in the sequences S1 to SK, all the second elements in the sequences S1 to SK, and so on until the Mth elements of the sequences S1 to SK, to form the interlaced scan order comprising K*M elements.

### Claim 3 (depends on 1)

The scan method as claimed in claim 1, wherein at least one of the sequences is determined based on accumulated power consumption of corresponding lines.

### Claim 4 (depends on 1)

The scan method as claimed in claim 1, wherein the shift value N1 is zero.

### Claim 5 (depends on 4)

The scan method as claimed in claim 4, wherein:
the shift values N2 to NK form a non-decreasing function ranging from 1 to M.

### Claim 6

A timing controller, for a liquid crystal display comprising a plurality of lines, wherein:
the timing controller divides Y lines into K groups;
the timing controller provides K sequences S1 to SK and interlaces the K sequences S1 to SK to determine an interlaced scan order;
the timing controller synchronously scans the K groups of lines based on the interlaced scan order such that each group of lines is scanned K times per Y scan time slots and the each group of lines is scanned alternately and any two lines in each group of lines are not scanned at the same time in one scan slot;
K is an integer not less than 2, wherein:
Si(x)=(x+Ni)(mod M), i=1 to K, x=1 to M;
where Si(x) denotes the xth element in sequence Si.

### Claim 7 (depends on 6)

The timing controller as claimed in claim 6, wherein:
each group of lines comprises at least M lines;
the timing controller provides K shift values N1 to NK, wherein the shift values are not greater than M;
the timing controller determines the sequences S1 to SK based on the shift values N1 to NK; and
the timing controller sequentially selects all the first elements in the sequences S1 to SK, all the second elements in the sequences S1 to SK, and so on until the Mth elements of the sequences S1 to SK, to form the interlaced scan order comprising K*M elements.

### Claim 8 (depends on 6)

The timing controller as claimed in claim 6, wherein the timing controller determines at least one of the sequences based on accumulated power consumption of corresponding lines.

### Claim 9 (depends on 7)

The timing controller as claimed in claim 7, wherein:
(mod M) denotes a congruence residue operation that ensures the Si(x) to be a positive integer not exceeding M.

### Claim 10 (depends on 7)

The timing controller as claimed in claim 7, wherein the shift value N1 is zero.

### Claim 11 (depends on 10)

The timing controller as claimed in claim 10, wherein:
the shift values N2 to NK form a non-decreasing function ranging from 1 to M.

### Claim 12

A pixel driving circuit for a flat panel display, synchronously scanning Y lines divided into K groups, comprising:
K gate drivers, each driving a corresponding group of lines;
a timing controller, coupled to the K gate drivers, for controlling a processing order and image data; and
a frame memory, coupled to the timing controller, for storing the image data; wherein
the timing controller provides K sequences S1 to SK and interlaces the K sequences S1 to SK to determine an interlaced scan order;
the timing controller synchronously scans the K groups of lines based on the interlaced scan order via the K gate drivers such that each group of lines is scanned K times per Y scan time slots and the each group of lines is scanned alternately and any two lines in each group of lines are not scanned at the same time in one scan slot; and
K is an integer not less than 2, wherein:
Si(x)=(x+Ni)(mod M), i=1 to K, x=1 to M; and
where Si(x) denotes the xth element in sequence Si.

### Claim 13 (depends on 12)

The pixel driving circuit as claimed in claim 12, wherein:
each group of lines comprises at least M lines;
the timing controller provides K shift values N1 to NK, wherein the shift values are not greater than M;
the timing controller determines the sequences S1 to SK based on the shift values N1 to NK; and
the timing controller sequentially selects all the first elements in the sequences S1 to SK, all the second elements in the sequences S1 to SK, and so on until the Mth elements of the sequences S1 to SK, to form the interlaced scan order comprising K*M elements.

### Claim 14 (depends on 12)

The pixel driving circuit as claimed in claim 12, wherein the timing controller determines at least one of the sequences based on accumulated power consumption of corresponding lines.

### Claim 15 (depends on 13)

The pixel driving circuit as claimed in claim 13, wherein:
(mod M) denotes a congruence residue operation that ensures the Si(x) to be a positive integer not exceeding M.

### Claim 16 (depends on 15)

The pixel driving circuit as claimed in claim 15, wherein the shift value N1 is zero.

### Claim 17 (depends on 15)

The pixel driving circuit as claimed in claim 15, wherein:
the shift values N2 to NK form a non-decreasing function ranging from 1 to M.