# US 8,570,205 B2 · Analog to digital converter with leakage current correction circuit

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- Number: US 8,570,205 B2
- Document ID: US8570205B2
- Status: Granted
- Kind: B2
- Application number: 13/363,471
- Filed: 2012-02-01
- Published: 2013-08-01
- Granted: 2013-10-29
- Earliest claimed: 2012-02-01
- Assignees: Texas Instruments Incorporated
- Applicants: Maher Mahmoud Sarraj; Haydar Bilhan
- Inventors: Maher Mahmoud Sarraj; Haydar Bilhan
- Web page: https://patentgrep.com/patent/US8570205B2

## CPC

- H03F 3/005: {using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence)}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03K 17/162: {without feedback from the output circuit to the control circuit}
- H03M 1/06: Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10)
- H03K 2217/0054: Gating switches, e.g. pass gates
- H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array}
- H03F: AMPLIFIERS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current.

## Claims

### Claim 1

In an analog to digital converter having a switched capacitor digital to analog converter, a reset switch, a dummy transistor having a shape factor substantially identical to that of the reset switch and a comparator, a method of cancelling a leakage current induced by the reset switch comprising steps of:
(a) replicating a voltage appearing on an input sense node to the comparator onto a drain terminal on the dummy transistor to create a cancelling leakage current substantially similar to the leakage current induced by the reset switch; and,
(b) feeding back the cancelling leakage current to the input sense node of the comparator to cancel the leakage current.

### Claim 2 (depends on 1)

The method of claim 1 wherein the analog to digital converter includes a second reset switch and a second dummy transistor and steps (a)-(b) are performed for the second reset switch.

### Claim 3 (depends on 1)

The method of claim 1 wherein the reset switch is coupled between the input sense node and a voltage equal to substantially half the supply voltage.

### Claim 4 (depends on 1)

The method of claim 1 wherein the dummy transistor is a pMOS transistor.

### Claim 5 (depends on 1)

The method of claim 1 wherein the reset switch comprises a pMOS transistor and an nMOS transistor coupled in parallel with respective source and drain terminals coupled together.

### Claim 6

In an analog to digital converter having a switched capacitor digital to analog converter, a reset switch and a comparator, a leakage current correction circuit comprising:
a dummy transistor having a shape factor substantially identical to that of the reset switch;
circuitry to replicate a voltage appearing on an input sense node to the comparator onto a drain terminal on the dummy transistor to create a cancelling leakage current substantially similar to the leakage current induced by the reset switch; and,
circuitry to feed back the cancelling leakage current to the input sense node of the comparator to cancel the leakage current.

### Claim 7

An analog to digital converter comprising:
a switched capacitor digital to analog converter;
at least one reset switch;
a comparator, and,
at least one leakage current correction circuit having a dummy transistor with a shape factor substantially identical to that of the at least one reset switch and circuitry to replicate a voltage appearing on an input sense node to the comparator onto a drain terminal on the dummy transistor to create a cancelling leakage current substantially similar to the leakage current induced by the reset switch and circuitry to feed back the cancelling leakage current to the input sense node of the comparator to cancel the leakage current.

### Claim 8 (depends on 7)

The analog to digital converter of claim 7 wherein the at least one reset switch is coupled between the input node and a voltage substantially one half the voltage supply rail.

### Claim 9 (depends on 7)

The analog to digital converter of claim 7 wherein the at least one leakage current correction circuit includes a plurality of correction circuits.

### Claim 10 (depends on 7)

The analog to digital converter of claim 7 wherein the switched capacitor digital to analog converter comprises an array of individually switched, binary-weighted capacitors in combination with a resistor divider array.

### Claim 11 (depends on 7)

The analog to digital converter of claim 7 wherein the switched capacitor digital to analog converter has a differential input.

### Claim 12

A leakage current correction circuit comprising:
an operational amplifier having an inverting input, a non-inverting input and an output;
a first pMOS transistor having source, gate and drain terminals;
a second pMOS transistor having source, gate and drain terminals,
a first nMOS transistor having source, gate and drain terminals;
a second nMOS transistor having source, gate and drain terminals,
a third nMOS transistor having source, gate and drain terminals;
a fourth nMOS transistor having source, gate and drain terminals; wherein
the gate and drain terminals of the first pMOS transistor are connected to a positive supply voltage;
the drain terminal of the first pMOS transistor is connected to the source terminal of second pMOS transistor and to the inverting input of operational amplifier;
the gate terminal of the second pMOS transistor is connected to the output of operational amplifier;
the drain terminal of the second pMOS transistor is connected to the gate and the drain terminals of the first nMOS transistor and to the gate terminal of the second nMOS transistor;
the source terminal of the second nMOS transistor is connected to the drain terminal of the fourth nMOS transistor;
the non-inverting input of the operational amplifier is connected to the drain terminal of second nMOS transistor and to an input node on a comparator;
the source terminal of the first nMOS transistor is connected to the gate and the drain terminals of the third nMOS transistor and to the gate terminal of the fourth nMOS transistor;
the source terminal of the second nMOS transistor is connected to the drain terminal of the fourth nMOS transistor; and,
the source terminal of the third nMOS transistor and the fourth nMOS transistor are connected to a negative supply voltage.

### Claim 13 (depends on 12)

The leakage current correction circuit of claim 12 wherein the first nMOS transistor and second nMOS transistor have substantially similar transistor shape factors.

### Claim 14 (depends on 12)

The leakage current correction circuit of claim 12 wherein the third nMOS transistor and fourth nMOS transistor have substantially similar transistor shape factors.

### Claim 15 (depends on 12)

The leakage current circuit of claim 12 wherein the first nMOS transistor, second nMOS transistor, third nMOS transistor and fourth nMOS transistor have substantially similar transistor shape factors.