# US 8,570,204 B2 · Folded reference voltage flash ADC and method thereof

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- Number: US 8,570,204 B2
- Document ID: US8570204B2
- Status: Granted
- Kind: B2
- Application number: 13/527,406
- Filed: 2012-06-19
- Published: 2013-01-03
- Granted: 2013-10-29
- Earliest claimed: 2011-06-30
- Assignees: Electronics and Telecommunications Research Institute; Korea Advanced Institute of Science and Technology
- Applicants: Hyun-Min Bae; Soon-Won Kwon; Se-Jun Jeon
- Inventors: Hyun-Min Bae; Soon-Won Kwon; Se-Jun Jeon
- Web page: https://patentgrep.com/patent/US8570204B2

## CPC

- H03M 1/141: {in which at least one step is of the folding type; Folding stages therefore}
- H03M 1/361: {having a separate comparator and reference value for each quantisation level, i.e. full flash converter type}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A folded reference voltage flash analog-to-digital (ADC) converter and a method thereof are provided. The flash ADC of the present invention determines the most significant bit (MSB) of an analog input signal, varies a reference voltage input to a plurality of comparators in accordance with the MSB determination result, and determines the remaining bits. Accordingly, input capacitance can be reduced while maintaining the size and power consumption of the ADC.

## Claims

### Claim 1

A flash analog-to-digital converter (ADC), comprising:
a first ADC unit that determines a most significant bit (MSB) of an analog input signal;
a second ADC unit that includes a plurality of comparators that receive the analog input signal and a reference voltage and determine remaining bits of the analog input signal; and
a reference voltage control unit that varies the reference voltage input to the second ADC unit in accordance with the MSB determination result of the first ADC unit.

### Claim 2 (depends on 1)

The flash ADC according to claim 1, wherein the first ADC unit receives the analog input signal and determines the MSB as “1” when the input analog input signal is larger than “0” and as “0” when the input analog input signal is less than “0”.

### Claim 3 (depends on 1)

The flash ADC according to claim 1, wherein the reference voltage control unit sets the reference voltage input to the plurality of comparators of the second ADC unit as a positive value larger than “0” when the MSB is determined as “1” in accordance with the MSB determination result of the first ADC unit, and sets the reference voltage as a negative value less than “0” when the MSB is determined as “0”.

### Claim 4 (depends on 1)

The flash ADC according to claim 1, wherein the reference voltage control unit changes the reference voltage to a positive value or a negative value by inputting the reference voltage to the plurality of comparators of the second ADC unit in which positions of (+) and (−) terminals are changed.

### Claim 5 (depends on 4)

The flash ADC according to claim 4, wherein the reference voltage control unit enables the reference voltage having a positive value and the reference voltage having a negative value to share a single comparator by changing the positions of (+) and (−) terminals, thereby reducing an input capacitance.

### Claim 6 (depends on 1)

The flash ADC according to claim 1, wherein the second ADC unit includes a comparator having interpolation.

### Claim 7

A flash analog-to-digital conversion method, comprising:
determining a MSB of an analog input signal;
varying a reference voltage input to a plurality of comparators in accordance with the MSB determination result; and
receiving the analog input signal and the varied reference voltage and determining remaining bits of the analog input signal using the plurality of comparators.

### Claim 8 (depends on 7)

The flash analog-to-digital conversion method according to claim 7, wherein in determining the MSB, the MSB is determined as “1” when the input analog input signal is larger than “0” and is determined as “0” when the analog input signal is less than “0”.

### Claim 9 (depends on 7)

The flash analog-to-digital conversion method according to claim 7, wherein in varying the reference voltage, the reference voltage input to the plurality of comparators is set as a positive value larger than “0” when the MSB is determined as “1” and set as a negative value less than “0” when the MSB is determined as “0”.

### Claim 10 (depends on 7)

The flash analog-to-digital conversion method according to claim 7, wherein in varying the reference voltage, the reference voltage is changed to a positive value or a negative value by inputting the reference voltage to the plurality of comparators in which positions of (+) and (−) terminals are changed.