# US 8,570,202 B2 · Digital-to-analog converter implementing hybrid conversion architecture

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- Number: US 8,570,202 B2
- Document ID: US8570202B2
- Status: Granted
- Kind: B2
- Application number: 13/365,883
- Filed: 2012-02-03
- Published: 2013-08-08
- Granted: 2013-10-29
- Earliest claimed: 2012-02-03
- Assignees: SiGear Europe Sarl
- Applicants: Alain-Serge Porret; Friederich Mombers; Melly Thierry
- Inventors: Alain-Serge Porret; Friederich Mombers; Melly Thierry
- Web page: https://patentgrep.com/patent/US8570202B2

## CPC

- H03M 3/50: {Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004)}
- H03M 1/682: {both converters being of the unary decoded type}
- H03M 3/338: {by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A digital-to-analog converter (DAC) implements a hybrid conversion architecture where the input digital data is oversampled and a flash converter is used to convert the M most significant bits (MSBs) of the oversampled data while a sigma-delta (Σ-Δ) converter is used to convert the remaining least significant bits (LSBs) of the oversampled data. In one embodiment, a merged flash converter is used to convert the M MSBs and the digital bit stream generated by the sigma-delta converter.

## Claims

### Claim 1

A digital-to-analog converter (DAC) circuit receiving an N1-bit digital input data at a first sampling frequency and generating an analog output signal indicative of the digital input data, the DAC circuit comprising:
a rate converter configured to receive the N1-bit digital input data and to generate an oversampled output data in N2 bits at an oversampled frequency being K times the first sampling frequency;
a first converter configured to receive M most significant bits (MSBs) of the oversampled output data and to generate a first analog signal indicative of the M MSBs of the oversampled output data;
a sigma-delta converter configured to receive N2-M least significant bits (LSBs) of the oversampled output data and to generate a second analog signal indicative of the N2-M LSBs of the oversampled output data;
a data combiner configured to combine the first and second analog signals and to generate a third analog signal; and
an anti-aliasing filter configured to filter the third analog signal to generate a filtered analog output signal as the analog output signal of the DAC circuit.

### Claim 2 (depends on 1)

The DAC circuit of claim 1, wherein N2 is less than N1.

### Claim 3 (depends on 1)

The DAC circuit of claim 1, wherein the N1-bit digital input data comprises an N1-bit binary-weighted digital input data and the first converter comprises a binary-weighted flash converter.

### Claim 4 (depends on 1)

The DAC circuit of claim 1, wherein the sigma-delta converter comprises a sigma-delta modulator configured to process the N2-M LSBs into a P-states digital bit stream, P being 2 or more, and a second converter configured to receive the P-states digital bit stream and to generate the second analog signal.

### Claim 5 (depends on 4)

The DAC circuit of claim 4, wherein the second converter comprises a thermometric flash converter.

### Claim 6 (depends on 4)

The DAC circuit of claim 4, wherein the N2-M LSBs has an input range of a first value and the sigma-delta modulator comprises a sigma-delta modulator having an output range of a second value, the second value being greater than the first value.

### Claim 7 (depends on 6)

The DAC circuit of claim 6, wherein the sigma-delta modulator comprises a single-bit sigma-delta modulator with P=2 and two output levels and with an output weight being a multiple of the least significant bit of the M MSBs to extend the output range to be greater than the input range.

### Claim 8 (depends on 6)

The DAC circuit of claim 6, wherein the sigma-delta modulator comprises a multi-bit sigma-delta modulator where P is 3 or more and the sigma-delta modulator is configured to generate the digital bit stream having three or more states corresponding to three or more output levels.

### Claim 9 (depends on 8)

The DAC circuit of claim 8, wherein the sigma-delta modulator comprises a 1.5-bit sigma-delta modulator configured to generate the digital bit stream having three states (P=3) and three output levels.

### Claim 10 (depends on 4)

The DAC circuit of claim 4, wherein the sigma-delta modulator implements a second order noise shaping filter.

### Claim 11 (depends on 4)

The DAC circuit of claim 4, further comprising a delay circuit configured to receive the M MSBs of the oversampled output data and to introduce a delay to the M MSBs before providing the delayed M MSBs to the first converter, the delay provided by the delay circuit matching a signal propagation delay through the sigma-delta modulator.

### Claim 12

A digital-to-analog converter (DAC) circuit receiving an N1-bit digital input data at a first sampling frequency and generating an analog output signal indicative of the digital input data, the DAC circuit comprising:
a rate converter configured to receive the N1-bit digital input data and to generate an oversampled output data in N2 bits at an oversampled frequency being K times the first sampling frequency;
a sigma-delta modulator configured to receive N2-M least significant bits (LSBs) of the oversampled output data and to process the N2-M LSBs into a P-state digital bit stream, P being 2 or more;
a data combiner configured to receive and combine M most significant bits (MSBs) of the oversampled output data and the P-states digital bit stream into a set of combined data bits;
a converter configured to receive the set of combined data bits and to generate a first analog signal; and
an anti-aliasing filter configured to filter the first analog signal to generate a filtered analog output signal as the analog output signal of the DAC circuit.

### Claim 13 (depends on 12)

The DAC circuit of claim 12, wherein N2 is less than N1.

### Claim 14 (depends on 12)

The DAC circuit of claim 12, wherein the N2-M LSBs has an input range of a first value and the sigma-delta modulator comprises a sigma-delta modulator having an output range of a second value, the second value greater than the first value.

### Claim 15 (depends on 14)

The DAC circuit of claim 14, wherein the sigma-delta modulator comprises a single-bit sigma-delta modulator with P=2 and two output levels and with an output weight being a multiple of the least significant bit of the M MSBs to extend the output range to be greater than the input range.

### Claim 16 (depends on 14)

The DAC circuit of claim 14, wherein the sigma-delta modulator comprises a multi-bit sigma-delta modulator where P is 3 or more and the sigma-delta modulator is configured to generate the digital bit stream having three or more states corresponding to three or more output levels.

### Claim 17 (depends on 16)

The DAC circuit of claim 16, wherein the sigma-delta modulator comprises a 1.5-bit sigma-delta modulator configured to generate the digital bit stream having three states (P=3) and three output levels.

### Claim 18 (depends on 12)

The DAC circuit of claim 12, wherein the sigma-delta modulator implements a second order noise shaping filter.

### Claim 19 (depends on 12)

The DAC circuit of claim 12, further comprising a delay circuit configured to receive the M MSBs of the oversampled output data and to introduce a delay to the M MSBs before providing the delayed M MSBs to the first converter, the delay provided by the delay circuit matching a signal propagation delay through the sigma-delta modulator.

### Claim 20 (depends on 12)

The DAC circuit of claim 12, wherein the converter comprises a thermometric flash converter.

### Claim 21 (depends on 20)

The DAC circuit of claim 20, wherein the flash converter comprises a bank of switched current sources having identical current values, the switched current sources being controlled by the set of combined data bits to supply currents to an output node, the sum of the currents at the output node being indicative of the first analog signal.

### Claim 22 (depends on 20)

The DAC circuit of claim 20, wherein the set of combined data bits are in binary form and are converted to thermometric codes, the thermometric-code-converted data bits being used to control the bank of switched current sources.

### Claim 23 (depends on 22)

The DAC circuit of claim 22, further comprises a barrel shifter configured to receive the set of combined data bits in binary form, the barrel shifter being configured to convert the combined data bits to thermometric codes and to apply the thermometric-code-converted data bits in rotation to each of the switched current sources.