# US 8,570,100 B2 · Direct sampling circuit and receiver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,100 B2 - Document ID: US8570100B2 - Status: Granted - Kind: B2 - Application number: 13/122,475 - Filed: 2010-08-30 - Published: 2011-08-18 - Granted: 2013-10-29 - Earliest claimed: 2009-08-31 - Assignees: Panasonic Corporation - Applicants: Yohei Morishita; Noriaki Saito - Inventors: Yohei Morishita; Noriaki Saito - Web page: https://patentgrep.com/patent/US8570100B2 ## CPC - H03H 15/023: {with parallel-input configuration} - H04B 1/0007: {wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H04B: TRANSMISSION ## Abstract A sampling circuit and a receiver, with relatively simple configurations, and clocks, exhibiting excellent frequency characteristics, are provided. In discrete time circuits, a charging switch is controlled on and off using one of four-phase control signals. A rotate capacitor shares electrical charge accumulated in an IQ generating circuit via the charging switch. A dump switch is controlled on and off using a different signal from the control signal used to control the charging switch on and off, among the four-phase control signals. A buffer capacitor shares electrical charge with the rotate capacitor via the dump switch to form an output value. ## Claims ### Claim 1 A sampling circuit, comprising: a clock generating circuit that outputs four-phase control signals according with a period of a carrier frequency of an input signal; an IQ generating circuit that samples the input signal according to the four-phase control signals, and accumulates four kinds of sample values having different phases as electrical charge; and a group of discrete time circuits including a first to a fourth discrete time circuits that share electrical charge of the four kinds of sample values, respectively, wherein: each of the first to the fourth discrete time circuits includes: a charging switch; a rotate capacitor connected to the IQ generating circuit via the charging switch; a dump switch; and a buffer capacitor connected to the rotate capacitor via the dump switch; the charging switch is controlled on and off using any one of the four-phase control signals; the rotate capacitor shares electrical charge accumulated in the IQ generating circuit via the charging switch; the dump switch is controlled on and off using another one of the four-phase control signals having a different phase from the four-phase control signal used by the charging switch; and the buffer capacitor forms an output value by sharing electrical charge with the rotate capacitor via the dump switch. ### Claim 2 (depends on 1) The sampling circuit according to claim 1, further comprising: a coupling circuit that couples electrical charge of the four kinds of sample values having different phases, wherein, during a period the charging switch is turned on, the rotate capacitor shares electrical charge accumulated in the IQ generating circuit and electrical charge coupled by the coupling circuit. ### Claim 3 (depends on 2) The sampling circuit according to claim 2, wherein: the IQ generating circuit includes: a first IQ generating circuit that accumulates four types of positive-phase sample values having different phases as electrical charge by sampling a positive-phase input signal; and a second IQ generating circuit that accumulates four types of negative-phase sample values having different phases as electrical charge by sampling a negative-phase input signal; the coupling circuit includes: a first coupling circuit that couples electrical charge of a first, a second, a third and a fourth types of the positive-phase sample values; and a second coupling circuit that couples electrical charge of a first, a second, a third and a fourth types of the negative-phase sample values; and the group of discrete time circuits includes: a first group of discrete time circuits connected to the first IQ generating circuit; and a second group of discrete time circuits connected to the second IQ generating circuit. ### Claim 4 (depends on 2) The sampling circuit according to claim 2, wherein: the IQ generating circuit includes: a first IQ generating circuit that accumulates four types of positive-phase sample values having different phases, as electrical charge, by sampling a positive-phase input signal; and a second IQ generating circuit that accumulates four types of negative-phase sample values having different phases, as electrical charge, by sampling a negative-phase input signal; the coupling circuit includes: a first coupling circuit that couples electrical charge of a first and a third types of positive-phase sample values with electrical charge of a second and a fourth types of negative-phase sample values; and a second coupling circuit that couples electrical charge of a second and a fourth types of positive-phase sample values with electrical charge of a first and a third types of negative-phase sample values; and the group of discrete time circuit includes: a first group of discrete time circuits connected to the first IQ generating circuit; and a second group of discrete time circuits connected to the second IQ generating circuit. ### Claim 5 (depends on 2) The sampling circuit according to claim 2, wherein: the coupling circuit includes: one capacitor; and four switches that control to turn on and off a current of the four kinds of sample values having different phases, to the capacitor; wherein the clock generating circuit generates, as the control signals, four-phase signals which have a duty ratio of 25% and have phases ¼ shifted from each other, and outputs the control signals which are high at different timings, to the four switches, respectively. ### Claim 6 (depends on 2) The sampling circuit according to claim 2, wherein the coupling circuit has one capacitor and is connected between the transconductance amplifier and the sampling switch. ### Claim 7 (depends on 1) The sampling circuit according to claim 1, wherein: the IQ generating circuit includes: a transconductance amplifier that converts the input signal from a voltage signal to a current signal and outputs the current signal; four sampling switches that sample the current signal according to the four-phase control signals, and output four kinds of current signals; and four history capacitors that accumulate four kinds of electrical charge supplied by sampled current signals, each of the first to the fourth discrete time circuits further includes: a reset switch that controls to accumulate or discharge electrical charge in the rotate capacitor; and a precharge switch that controls a voltage of the rotate capacitor, wherein the charging switch, the dump switch, the reset switch and the precharge switch are controlled on and off in this order, using the four-phase control signals. ### Claim 8 (depends on 7) The sampling circuit according to claim 7, wherein each of the four sampling switches samples the current signal according to a designated four-phase control signal corresponding to one and only one of the four sampling switches. ### Claim 9 (depends on 7) The sampling circuit according to claim 7, wherein each of the four sampling switches connects to a charging switch included in a corresponding discrete time circuit, and the each of the four sampling switches and the charging switch included in the corresponding discrete time circuit are controlled using one of the four-phase control signals. ### Claim 10 (depends on 1) The sampling circuit according to claim 1, wherein the clock generating circuit generates, as the control signals, four-phase signals which have a same period as a period of a carrier frequency of the input signal, have a duty ratio of 25%, have phases a ¼ period shifted from each other, and outputs the control signals which are high at different timings, to four sampling switches, respectively. ### Claim 11 (depends on 1) The sampling circuit according to claim 1, wherein: each of the switches has a set of two sub-switches serially connected; and the clock generating circuit: generates, as the control signals, two-phase first and second signals which have a same period as a period of a carrier frequency of the input signal, have a duty ratio of 50% and have phases a ½ period shifted from one another, and two-phase third and fourth signals which have a period ½ of the period of the carrier frequency of the input signal, have a duty ratio of 50% and have phases shifted from the carrier frequency by a ¼ period; and outputs the first or second signal to one of the two sub-switches serially connected, and outputs the third or fourth signal to the other. ### Claim 12 (depends on 1) A receiver, comprising: a sampling circuit according to claim 1; an antenna that receives an input signal; a low noise amplifier that amplifies a signal received by the antenna and outputs an amplified signal to the sampling circuit; and an analog-to-digital converting section that converts an output signal from the sampling circuit, from an analog signal to a digital signal. ### Claim 13 (depends on 12) The receiver according to claim 12, wherein: the receiver is a low-intermediate frequency receiver; and the sampling circuit outputs a signal in a low-intermediate frequency band, as the output signal. ### Claim 14 (depends on 13) A diversity receiver, comprising: a plurality of receivers; and a digital processing section that selectively synthesizes digital outputs from the plurality of receivers, wherein at least one of the plurality of receivers includes the receiver according to claim 13.