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US 8,570,086 B2Granted
Delay latch circuit and delay flip-flop
AssigneeSony Corporation
InventorKoji Hirairi
Life of this patent
Estimating the term…
Abstract
Disclosed herein are a delay latch circuit and a delay flip-flop circuit arranged to inhibit the increase in power consumption while preventing malfunction under low voltage conditions. An internal signal output circuit outputs as an internal signal an inverted signal of a data signal starting from an internal transparency start timing until an internal transparency end timing. From the internal transparency end timing until the internal transparency start timing, the internal signal output circuit outputs a fixed value signal as the internal signal. A transistor delays the output internal signal over a time period which ranges from a hold instruction delay timing to the issuance of a data transparency instruction and which includes the internal transparency end timing therebetween.
Claims24
A circuit comprising:
- a first delay latch circuit that includes a first internal signal generation portion and a first data hold portion, wherein
- the first internal signal generation portion includes a first NOR gate, the first NOR gate including a first input connected to a first data signal line and a second input connected to a clock signal line, and
- the first data hold portion includes a second NOR gate and a third NOR gate, the second NOR gate including a first input connected to an output node of the first NOR gate and a second input connected to an output node of the third NOR gate, and the third NOR gate including a first input connected to an inverted clock signal line and a second input connected to an output node of the second NOR gate, wherein
- the first NOR gate includes a first internal signal output circuit and a first delay transistor, the first delay transistor being configured to delay a signal output from the first inter signal output circuit.
1 more element
A circuit comprising:
- first delay latch that includes a first internal signal generation portion and a data hold portion, wherein
- the first internal signal generation portion includes a first NOR gate, the first NOR gate including a first input connected to a first data signal line and a second input connected to a clock signal line, and
- the first data hold portion includes a second NOR gate and a third NOR gate, the second NOR gate including a first input connected to an output node of the first NOR gate and a second input connected to an output node of the third NOR gate, and the third NOR gate including a first input connected to an inverted clock signal line and a second input connected to an output node of the second NOR gate;
- and
- a second delay latch circuit that includes a second internal signal generation portion and a second data hold portion, wherein
- the second internal signal generation portion includes a first NAND gate, the first NAND gate including a first input connected to an output of a third inverter, an input of the third inverter being connected to the output node of the second NOR gate, and the first NAND gate including a second input node connected to the clock signal line, and
- the second data hold portion includes a second NAND gate and a third NAND gate, the second NAND gate including a first input connected to an output node of the first NAND gate and a second input connected to an output node of the third NAND gate, and the third NAND gate including a first input connected to the inverted clock signal line and a second input connected to an output node of the second NAND gate.
4 more elements
A circuit comprising:
- a first delay latch circuit that includes a first internal signal generation portion and a first data hold portion, wherein
- the first internal signal generation portion includes a first NAND gate, the first NAND gate including a first input connected to a first data signal line and a second input connected to a clock signal line, and
- the first data hold portion includes a second NAND gate and a third NAND gate, the second NAND gate including a first input connected to an output node of the first NAND gate and a second input connected to an output node of the third NAND gate, and the third NAND gate including a first input connected to an inverted clock signal line and a second input connected to an output node of the second NAND gate;
- and
- a second delay latch circuit that includes a second internal signal generation portion and a second data hold portion, wherein
- the second internal signal generation portion includes a first NOR gate, the first NOR gate including a first input connected to an output of a third inverter, an input of the third inverter being connected to the output node of the second NAND gate, and the first NAND gate including a second input node connected to the clock signal line, and
- the second data hold portion includes a second NOR gate and a third NOR gate, the second NOR gate including a first input connected to an output node of the first NOR gate and a second input connected to an output node of the third NOR gate, and the third NOR gate including a first input connected to the inverted clock signal line and a second input connected to an output node of the second NOR gate.
4 more elements
A circuit comprising:
- a first delay latch circuit includes a first internal signal generation portion and a first data hold portion, wherein
- the first internal signal generation portion includes a first NAND gate, the first NAND gate including a first input connected to a first data signal line and a second input connected to an inverted clock signal line, and
- the first data hold portion includes a second NAND gate and first OR gate, the second NAND gate including a first input connected to an output node of the first NAND gate and a second input connected to an output node of the first OR gate, and the first OR gate including a first input connected to the inverted clock signal line and a second input connected to an output node of the second NAND gate;
- and
- a second delay latch circuit that includes a second internal signal generation portion and a second data hold portion, wherein
- the second internal signal generation portion includes a third NAND gate, the third NAND gate including a first input connected to the output node of the second NAND gate and second input connected to a clock signal line, and
- the second data hold portion includes a fourth NAND gate and second NOR gate, the fourth NAND gate including a first input connected to an output node of the third NAND gate and a second input connected to an output node of the second NOR gate, and the second NOR gate including a first input connected to the clock signal line and a second input connected to an output node of the fourth NAND gate.
4 more elements
A circuit comprising:
- a first delay latch circuit that includes a first internal signal generation portion and a data hold portion, wherein
- the first internal signal generation portion includes a first NOR gate, the first NOR gate including a first input connected to a first data signal line and a second input connected to a clock signal line, and
- the first data hold portion includes a first NAND gate and a first OR gate, the first NAND gate including a first input connected to an output node of the first NOR gate and a second input connected to an output node of the first OR gate, and the first OR gate including a first input connected to the clock signal line and a second input connected to an output node of the first NAND gate;
- and
- a second delay latch circuit that includes a second internal signal generation portion and a second data hold portion, wherein
- the second internal signal generation portion includes a second NOR gate, the second NOR gate including a first input connected to the output node of the first NAND gate and second input connected to an inverted clock signal line, and
- the second data hold portion includes a second NAND gate and second OR gate, the second NAND gate including a first input connected to an output node of the second OR gate and a second input connected to an output node of the second NOR gate, and the second OR gate including a first input connected to the inverted clock signal line and a second input connected to an output node of the second NAND gate.
4 more elements
Dependencies are inferred from the claim text.