Circuits and methods for clock signal duty-cycle correction
AssigneeMicron Technology, Inc.
InventorFeng Lin
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Abstract
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.
Claims20
A duty-cycle corrector, comprising:
- a driver configured to receive a differential signal and generate a single-ended input signal based, at least in part, on a first control signal;
- a clock tree configured to receive a delayed input signal, the delayed input signal based, at least in part, on the single-ended input signal delayed by a first time, the first time based, at least in part, on a second control signal, the clock tree further configured to delay the delayed input signal a second time to provide at least one of a first feedback signal or a second feedback signal;
- and
- a phase detector coupled to the clock tree and configured to provide the first control signal based, at least in part, on a phase difference between a first output signal and the first feedback signal, the phase detector further configured to provide the second control signal based, at least in part, on a second output signal and the second feedback signal.
An apparatus, comprising:
- a first driver configured to receive a differential signal and provide a first single-ended input signal based on a first control signal, wherein the first single-ended signal is converted into a first clock signal and a second clock signal, wherein the second clock signal is a complement to the first clock signal;
- a second driver configured to receive the differential signal and provide a second single-ended input signal based on the first control signal;
- a first clock tree model configured to receive the first single-ended input signal, the first clock tree configured to delay the first single-ended input signal a delay time based on a second control signal to provide a first feedback signal;
- a second clock tree model configured to receive the second single-ended input signal, the second clock tree configured to delay the second single-ended input signal the delay time based on a second control signal to provide a second feedback signal;
- and
- a phase detector coupled to the driver, to the first clock tree model, and to the second clock tree model, the phase detector configured to provide the second control signal in a first mode, the second control signal based a comparison of the first feedback signal and the first clock signal, the phase detector further configured to provide the first control signal in a second mode, the first control signal based on a comparison of the second clock signal and the second feedback signal.
A method, comprising:
- providing a first single-ended signal and a second single-ended signal at a duty-cycle correction circuit;
- delaying the first single-ended signal a delay time to produce a first feedback signal;
- delaying the second single-ended signal the delay time to produce a second feedback signal;
- providing a first control signal based on the first feedback signal and a first clock signal, wherein the first clock signal is based on the first single-ended signal;
- adjusting the delay time based on the second control signal;
- providing a second control signal based on a second clock signal and the second feedback signal, wherein the second clock signal is based on the first single-ended signal, wherein the second clock signal is a complement of the first clock signal;
- and
- adjusting the first single-ended signal and the second single-ended signal based on the first control signal.
Dependencies are inferred from the claim text.