# US 8,570,082 B1 · PVT-free calibration circuit for TDC resolution in ADPLL

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- Number: US 8,570,082 B1
- Document ID: US8570082B1
- Status: Granted
- Kind: B1
- Application number: 13/778,478
- Filed: 2013-02-27
- Granted: 2013-10-29
- Earliest claimed: 2013-02-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co. Ltd.
- Inventors: Feng Wei Kuo; Kuang-Kai Yen; Huan-Neng Chen; Hsien-Yuan Liao; Lee Tsung Hsiung; Chewn-Pu Jou; Robert Bogdan Staszewski
- Web page: https://patentgrep.com/patent/US8570082B1

## CPC

- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H03L 1/00: Stabilisation of generator output against variations of physical values, e.g. power supply
- H03L 7/16: Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L 2207/50: All digital phase-locked loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

The present disclosure relates to an all digital phase locked loop (APDLL) that can account for variations in PVT conditions, and a related method of formation. In some embodiments, the ADPLL has a controllable time-to-digital converter (TDC) having a plurality of variable delay elements. The controllable TDC is determines a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a phase error therefrom. A digitally controlled oscillator (DCO) varies a phase of the local oscillator clock signal based upon the phase error. A calibration unit determines an effect of variations in PVT (process, voltage, and temperature) conditions based upon the phase error and to generate a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to account for the variations in PVT conditions.

## Claims

### Claim 1

An all digital phase locked loop (ADPLL), comprising:
a controllable time-to-digital converter (TDC) configured to determine a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a variable phase therefrom;
a digitally controlled oscillator (DCO) configured to vary the phase of the local oscillator clock signal based upon the variable phase; and
a calibration unit configured to determine an effect of variations in PVT (process, voltage, and temperature) conditions based upon the variable phase, and to generate a TDC tuning word that adjusts a resolution of the controllable TDC to account for the effect of variations in PVT conditions.

### Claim 2 (depends on 1)

The ADPLL of claim 1, further comprising:
a phase detector configured to determine a phase error comprising a difference between the variable phase and a reference phase received from a reference phase accumulator; and
a digital loop filter is configured to receive a phase error and to generate a control word from the phase error, which controls operation of the DCO.

### Claim 3 (depends on 2)

The ADPLL of claim 2, further comprising:
a control unit configured to turn off power to the calibration unit if the phase error is within a first threshold value of an acceptable phase error.

### Claim 4 (depends on 2)

The ADPLL of claim 2, further comprising:
a memory element configured to store one or more TDC tuning words if the phase error is within a first threshold value of an acceptable phase error.

### Claim 5 (depends on 2)

The ADPLL of claim 2, wherein the calibration unit is configured to vary the resolution of the controllable TDC in a manner proportional to the phase error.

### Claim 6 (depends on 2)

The ADPLL of claim 2, wherein the calibration unit comprises:
a multiplexor configured to receive the phase error and an inverted phase error having an opposite sign of the phase error;
a logical NOR gate configured to generate a control signal provides an output of the multiplexor to a first filtering element configured to generate an error in the TDC tuning word; and
a second filtering element configured to receive the error in the TDC tuning word and to generate an updated TDC tuning word from the error in the TDC tuning word.

### Claim 7 (depends on 2)

The ADPLL of claim 2, wherein the digitally controlled TDC comprises:
a TDC core configured to receive the TDC tuning word, the local oscillator clock signal, and the frequency reference signal, and to determine a time difference between the local oscillator clock signal and the frequency reference signal that varies as a function of the TDC tuning word; and
a normal TDC configured to compare an output of the TDC core to a target resolution, wherein if the target resolution is not equal to the TDC resolution the normal TDC varies a value of the variable phase based upon the comparison.

### Claim 8 (depends on 7)

The ADPLL of claim 7, wherein the TDC core comprises:
a first delay chain comprising a plurality of delay elements connected in series, wherein the first delay chain is configured to receive the frequency reference signal;
a second delay chain comprising a plurality of delay elements connected in series, wherein the second delay chain is configured to receive the local oscillator clock signal;
a variable delay chain connected in parallel with the second delay chain and comprising a plurality of programmable delay elements; and
a variable capacitor chain connected in parallel with the second delay chain and comprising a plurality of switchable capacitors.

### Claim 9 (depends on 8)

The ADPLL of claim 8, wherein:
the TDC tuning word is configured to selectively operate a number of the programmable delay elements or the digitally controlled switch capacitors to vary achieve a resolution corresponding to the phase error.

### Claim 10 (depends on 7)

The ADPLL of claim 7, wherein the TDC core comprises:
a first delay chain comprising a plurality of delay elements connected in series, wherein the first delay chain is configured to receive the clock signal;
a second delay chain comprising a plurality of delay elements connected in series, wherein the second delay chain is configured to receive the reference signal;
a variable delay chain connected in parallel with the second delay chain and comprising a plurality of programmable delay elements; and
a variable capacitor chain connected in parallel with the second delay chain and comprising a plurality of switchable capacitors.

### Claim 11 (depends on 1)

The ADPLL of claim 1,
wherein the controllable time-to-digital converter (TDC) comprises a plurality of variable delay elements; and
wherein the calibration unit is configured to vary the resolution of the controllable TDC by adjusting a value of a delay introduced by one or more of the plurality of variable delay elements.

### Claim 12 (depends on 1)

The APDLL of claim 1, wherein the calibration unit is configured to determine a number of stages by dividing a maximum period of the DCO by a target TDC resolution.

### Claim 13

An all digital phase locked loop (ADPLL), comprising:
a controllable time-to-digital converter (TDC) having a plurality of variable delay elements, wherein the controllable TDC is configured to determine a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a variable phase therefrom;
a phase detector configured to determine a phase error comprising a difference between the variable phase and a reference phase received from a reference phase accumulator;
a digitally controlled oscillator (DCO) configured to vary the phase of the local oscillator clock signal based upon the phase error; and
a calibration unit configured to determine an effect of variations in PVT (process, voltage, and temperature) conditions based upon the phase error, and to generate a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to mitigate the effect of the variations in PVT conditions.

### Claim 14 (depends on 13)

The ADPLL of claim 13, wherein the TDC tuning word comprises a multi-bit digital word.

### Claim 15

A method, comprising:
providing power to an all digital phase locked loop (APDLL) comprising a controllable time-to-digital converter (TDC) comprising a plurality of variable delay element;
operating the controllable TDC to determining a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a variable phase therefrom;
determining an effect of variations in PVT (process, voltage, and temperature) conditions based upon the variable phase; and
generating a TDC tuning word that adjusts a resolution of the controllable TDC to mitigate an effect of the variations in PVT conditions.

### Claim 16 (depends on 15)

The method of claim 15, wherein the TDC tuning word adjusts a delay introduced by one or more of the plurality of variable delay elements within the controllable TDC to mitigate the effect of the variations in PVT conditions.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
determining a maximum period of a digitally controlled oscillator configured to generate the local oscillator clock signal;
determining a target TDC resolution; and
dividing the maximum period of the digitally controlled oscillator by the target resolution to determine a number of active variable delay elements in the controllable TDC.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
determining a phase error comprising a difference between the variable phase and a reference phase received from a reference phase accumulator; and
determining a value of the TDC tuning word based upon the phase error.

### Claim 19 (depends on 18)

The method of claim 18, wherein the resolution is adjusted in a manner proportional to the phase error.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
storing the TDC tuning word if the phase error is within a first threshold value of an acceptable phase error.