# US 8,570,081 B2 · Fast measurement initialization for memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,081 B2 - Document ID: US8570081B2 - Status: Granted - Kind: B2 - Application number: 13/541,113 - Filed: 2012-07-03 - Published: 2012-11-01 - Granted: 2013-10-29 - Earliest claimed: 2006-12-04 - Assignees: Micron Technology, Inc. - Applicants: Yantao Ma - Inventors: Yantao Ma - Web page: https://patentgrep.com/patent/US8570081B2 ## CPC - H03L 7/0818: {the controlled phase shifter comprising coarse and fine delay or phase-shifting means} - H03L 7/08: Details of the phase-locked loop - H03L 7/0814: {the phase shifting device being digitally controlled} - H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input} - H03L 7/10: for assuring initial synchronisation or for broadening the capture range - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be determined adaptively based on a phase difference between a reference signal and a clock signal being delayed. Such adaptive decisions can be made during each feedback cycle, thereby making it possible to achieve a phase lock faster and more efficiently. In some embodiments, such adaptive functionality can be incorporated into existing circuits with minimal impact. ## Claims ### Claim 1 A method for phase-locking a clock signal to a reference signal in a delay-lock loop, the method comprising: obtaining a phase difference between a clock signal and a reference signal during a phase comparison cycle; and shifting the phase of the clock signal by a collective amount such that a locking of the clock signal occurs during the phase comparison cycle, the collective amount based at least in part on the obtained phase difference and a plurality of delay adjustments, each delay adjustment associated with an enable status, a delay adjustment value and a phase adjustment window, the collective amount determined by iteratively shifting the clock signal by the delay adjustment value when the delay adjustment is enabled and a phase difference is outside the phase adjustment window, and updating the phase difference and the enable status based on the shifting for each delay adjustment. ### Claim 2 (depends on 1) The method of claim 1 further comprising updating a control logic based on the updated enable status of each delay adjustment. ### Claim 3 (depends on 2) The method of claim 2 wherein the collective amount is further determined by detecting an increased phase difference and increasing the delay adjustment value based at least in part on the increased phase difference. ### Claim 4 (depends on 2) The method of claim 2 wherein the collective amount is further determined by applying the largest delay adjustment value that does not over compensate for the phase difference between the clock signal and the reference signal. ### Claim 5 (depends on 1) The method of claim 1 further comprising providing a control logic having the enable status for each of the plurality of delay adjustments. ### Claim 6 (depends on 1) The method of claim 1 wherein each delay adjustment includes one or more coarse delay adjustment values followed by one or more fine delay adjustment values. ### Claim 7 (depends on 1) The method of claim 1 wherein the plurality of delay adjustments includes at least one delay adjustment comprising one or more coarse delay adjustment values followed by one or more half-coarse delay adjustment values and at least one delay adjustment comprising one or more fine delay adjustment values. ### Claim 8 (depends on 1) The method of claim 1 wherein the plurality of delay adjustments includes at least one delay adjustment comprising one or more coarse delay adjustment values and at least one delay adjustment comprising one or more fine delay adjustment values. ### Claim 9 (depends on 1) The method of claim 1 wherein the method is performed during an initialization stage of a memory device. ### Claim 10 A phase-locking system, comprising: computer hardware including at least one processor; and computer-readable storage including computer-readable instructions that, when executed by the processor, cause the computer hardware to perform operations defined by the computer-executable instructions, the computer-executable instructions including: obtaining a phase difference between a clock signal and a reference signal during a phase comparison cycle; and shifting the phase of the clock signal by a collective amount of delay such that a locking of the clock signal occurs during the phase comparison cycle, the collective amount of delay based at least in part on the obtained phase difference and a plurality of delay adjustments, each delay adjustment associated with an enable status, a delay adjustment value and a phase adjustment window, the collective amount of delay determined by iteratively shifting the clock signal by the delay adjustment value when the delay adjustment is enabled and a phase difference is outside the phase adjustment window, and updating the phase difference and the enable status based on the shifting for each delay adjustment. ### Claim 11 (depends on 10) The system of claim 10 wherein the computer-executable instructions further include updating a control logic for a next delay adjustment cycle based on the updated enable status of each delay adjustment. ### Claim 12 (depends on 10) The system of claim 10 further comprising a control logic configured to store the enable status for each of the plurality of delay adjustments during a plurality of delay adjustment cycles. ### Claim 13 (depends on 10) The system of claim 10 further comprising a delay adjustment component configured to apply the collective amount of delay to the clock signal. ### Claim 14 (depends on 10) The system of claim 10 further comprising an error detection and correction component configured to detect an increased phase difference and increase the delay adjustment value based at least in part on the increased phase difference. ### Claim 15 A memory device comprising: a phase detection component configured to determine a phase difference between a clock signal and a reference signal during a phase comparison cycle; a decision component in communication with a control logic having an enable status, a delay adjustment value and a phase adjustment window for each of a plurality of delay adjustments during a plurality of delay adjustment cycles, the decision component configured to adaptively determine a collective amount of delay to be applied to the clock signal based on the obtained phase difference and the plurality of delay adjustments until locking of the clock signal occurs during the phase comparison cycle, the adaptively determined collective amount of delay determined by iteratively shifting the clock signal by the delay adjustment value when the delay adjustment is enabled and a phase difference is outside the phase adjustment window, and updating the phase difference and the enable status based on the shifting for each delay adjustment; and a control component configured to control the phase detection component and the decision component so as to effectuate the adaptively determined collective amount of delay, the control component further configured to update a delay-locked loop based on the adaptively determined collective amount of delay during the phase comparison cycle. ### Claim 16 (depends on 15) The memory device of claim 15 further comprising a delay component configured to apply the adaptively determined collective amount of delay to the clock signal. ### Claim 17 (depends on 16) The memory device of claim 16 further comprising a feedback component configured to receive the delayed clock signal and determine a new phase difference between the delayed clock signal and the reference signal. ### Claim 18 (depends on 16) The memory device of claim 16 wherein the delay component comprises a delay buffer configured to apply a multiple of a delay unit based on the adaptively determined collective amount of delay. ### Claim 19 (depends on 15) The memory device of claim 15 further comprising an error detection and correction component configured to detect an increased phase difference and increase the delay adjustment value based at least in part on the increased phase difference. ### Claim 20 (depends on 15) The memory device of claim 15 wherein the plurality of delay adjustments includes at least one delay adjustment comprising one or more coarse delay adjustment values and at least one delay adjustment comprising one or more fine delay adjustment values.