CDR circuit
AssigneeKabushiki Kaisha Toshiba
InventorKiyohito Sato
Life of this patent
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Abstract
A CDR circuit includes a clock recovery circuit that generates, from an external clock, a first clock with which data of a received data signal is to be sampled and a second clock with which an edge of the received data signal is to be sampled and adjusts phases of the first clock and the second clock. The CDR circuit includes a phase detecting circuit that outputs a result of sampling of the received data signal with the first clock as a data sampling result and a result of sampling of the received data signal with the second clock as an edge sampling result. The CDR circuit includes a result comparing circuit that determines that a false lock condition has occurred and outputs a false lock condition detection signal if the edge sampling result matches with the data pattern.
Claims19
A CDR circuit, comprising:
- a clock recovery circuit that generates, from an external clock, a first clock as a data sampling clock with which data of a received data signal is to be sampled and a second clock as an edge sampling clock with which an edge of the received data signal is to be sampled and adjusts phases of the first clock and the second clock;
- a phase detecting circuit that outputs a result of sampling of the received data signal with the first clock as a data sampling result and a result of sampling of the received data signal with the second clock as an edge sampling result;
- and
- a result comparing circuit that compares the edge sampling result with a preset data pattern, and determines that a false lock condition has occurred and outputs a false lock condition detection signal if the edge sampling result matches with the data pattern,
- wherein the clock recovery circuit
- adjusts the phases of the first clock and the second clock based on the data sampling result and the edge sampling result, and
- resets adjustment of the phases of the first clock and the second clock when the false lock condition detection signal is input to the clock recovery circuit.
A CDR circuit, comprising:
- a clock recovery circuit that generates a first clock as a data sampling clock with which data of a received data signal is to be sampled and a second clock as an edge sampling clock with which an edge of the received data signal is to be sampled and adjusts phases of the first clock and the second clock;
- a phase detecting circuit that outputs a result of sampling of the received data signal with the first clock as a data sampling result and a result of sampling of the received data signal with the second clock as an edge sampling result;
- and
- a result comparing circuit that compares the edge sampling result with a preset data pattern, and determines that a false lock condition has occurred and outputs a false lock condition detection signal if the edge sampling result matches with the data pattern.
Dependencies are inferred from the claim text.