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US 8,570,077 B2Granted
Methods and implementation of low-power power-on control circuits
AssigneeQUALCOMM Incorporated
InventorsChang Ki Kwon, Craig E. Borden, Steve J. Halter, Tirdad Sowlati
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Abstract
Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply.
Claims29
An apparatus comprising:
- a power detector circuit powered by a first voltage supply;
- at least one voltage level-shifting device coupled to a second voltage supply and configured to provide a test input to the power detector circuit;
- a discharge path to enable a discharge of an input of the power detector circuit, wherein the discharge path comprises a first resistor, a second resistor, a first n-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor;
- and
- wherein the power detector circuit is configured to determine a logical status of the second voltage supply based on the test input and to provide an output indicating the logical status.
2 more elements
An apparatus comprising:
- a power detector circuit powered by a first voltage supply;
- at least one voltage level-shifting device coupled to a second voltage supply and configured to provide a test input to the power detector circuit;
- a leakage control device powered by the second voltage supply and responsive to a voltage level of the first voltage supply;
- and
- wherein the power detector circuit is configured to determine a logical status of the second voltage supply based on the test input and to provide an output indicating the logical status.
2 more elements
An apparatus comprising:
- means for detecting voltages, wherein the means for detecting voltages is powered by a first voltage supply;
- means for stepping down voltages, wherein the means for stepping down voltages is coupled to a second voltage supply and is configured to step down a voltage of the second voltage supply and provide a test input to the means for detecting voltages responsive to the second voltage supply;
- boundary logic, wherein the boundary logic comprises a plurality of latching elements;
- and
- wherein the means for detecting voltages is configured to reference the test input to determine a logical status of the second voltage supply and to provide an output indicating the logical status.
2 more elements
An apparatus comprising:
- means for detecting voltages, wherein the means for detecting voltages is powered by a first voltage supply;
- means for stepping down voltages, wherein the means for stepping down voltages is coupled to a second voltage supply and is configured to step down a voltage of the second voltage supply and provide a test input to the means for detecting voltages responsive to the second voltage supply;
- and
- a plurality of input/output (I/O) buffers coupled to a pad voltage supply.
1 more element
A method comprising:
- powering a power detector circuit by a first voltage supply;
- receiving at a voltage level-shifting device a voltage from a second voltage supply;
- providing, by the voltage level-shifting device, a test input to the power detector circuit;
- referencing the test input with the power detector circuit to detect whether the second voltage supply meets a threshold voltage;
- determining a logical status of the second voltage supply in response to the test input and providing an output indicating the logical status;
- outputting a first output from the power detector circuit that indicates that the second voltage supply has reached the threshold voltage;
- and
- wherein the power detector circuit provides the first output to a test access port (TAP) controller.
5 more elements
A power-on control circuit comprising:
- a power detector circuit coupled to a core voltage supply;
- a voltage level-shifting device coupled to a pad voltage supply and configured to provide a test input to the power detector circuit, wherein the voltage level-shifting device is configured to step down a voltage of the pad voltage supply;
- a buffer stage coupled to the power detector circuit and to the core voltage supply;
- Joint Test Action Group (JTAG) logic coupled to the buffer stage;
- and
- wherein the buffer stage is configured to provide an output indicating a state of the pad voltage supply.
3 more elements
A method, comprising:
- a first step for powering a power detector circuit with a first voltage supply;
- a second step for receiving at a voltage level-shifting device a voltage from a second voltage supply and stepping down the voltage;
- a third step for providing, with the voltage level-shifting device, a test input to the power detector circuit;
- and
- a fourth step for determining, at a test access port (TAP) controller, whether the second voltage supply is powered.
2 more elements
Dependencies are inferred from the claim text.