Parallel path frequency divider circuit

A method comprising:

• generating an enable signal based on a first portion of a current of a local oscillating input signal, wherein the enable signal is divided down in frequency from the local oscillating input signal;
• communicating the enable signal to a high speed latch;
• and
• generating an output signal based on a second portion of the current of the local oscillating input signal and the enable signal, wherein the output signal is divided down in frequency from the local oscillating input signal;
• wherein the enable signal is generated by a plurality of first transistors and the high speed latch comprises a plurality of second transistors larger relative to the plurality of first transistors;
• and further wherein the first portion of the current is approximately half of a received current and the second portion of the current is remaining current of the received current.

A frequency divider comprising:

• a local oscillating input node that receives a first local oscillating input signal onto the frequency divider;
• and
• means for frequency dividing the first local oscillating input signal by a fixed integer thereby generating a frequency divided output signal, wherein the means includes a low power frequency divider that receives a first portion of the local oscillating input signal and a high speed latch that receives a second portion of the local oscillating input signal and an enable signal from the low power frequency divider;
• wherein the low power frequency divider comprises a plurality of divider transistors and the high speed latch comprises a plurality of latch transistors larger relative to the plurality of divider transistors;
• and further wherein approximately half of a current at the local oscillating input node is directed to the low power frequency divider and remaining current is directed to the high speed latch.