Phase adjustment apparatus and clock generator thereof and method for phase adjustment
AssigneeMStar Semiconductor, Inc.
InventorJiunn-Yih Lee
Life of this patent
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Abstract
A phase adjustment apparatus for providing a clock signal to a core circuit is provided. The core circuit is powered by a core voltage. The phase adjustment apparatus includes two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and generates the clock signal according to the phase control signals and the two original clock signals.
Claims9
A phase adjustment apparatus, for providing a clock signal to a core circuit powered by a core voltage, the phase adjustment apparatus comprising:
- two clock receiving ends, for respectively receiving two original clock signals having a same frequency while the two original clock signal possess two different phases;
- a plurality of digital receiving ends, for receiving a plurality of phase selection signals;
- a synthesizing circuit, for generating the clock signal according to the phase selection signals and the two original clock signals;
- wherein, the synthesizing circuit is powered by a first voltage lower than the core voltage.
A method for phase adjustment, for providing a clock signal to a core circuit, the core circuit being powered by a core voltage, the method comprising:
- generating two original clock signals according to a control voltage using voltage-controlled oscillation;
- providing the clock signal by synthesizing the two original clock signals according to a ratio, the two original clock signals having a same frequency while the two original clock signals possess different phases;
- providing a synthesizing circuit, for generating the clock signal according to the two original signals;
- and
- powering the synthesizing circuit by a first voltage;
- wherein, an amplitude of the clock signal is smaller than the core voltage, and the first voltage is smaller than the core voltage.
Dependencies are inferred from the claim text.