Logic circuit and semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsYutaka Shionoiri, Hidetomo Kobayashi
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Abstract
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
Claims20
A semiconductor device comprising:
- a logic circuit comprising a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer;
- wherein the first transistor and the second transistor are electrically connected to each other,
- wherein the second transistor comprises an oxide semiconductor layer including a channel formation region, and
- wherein the oxide semiconductor layer comprises crystals whose c-axis is in direction perpendicular to a surface of the oxide semiconductor layer.
A semiconductor device comprising:
- a flip-flop and an AND gate electrically connected to each other, at least one of the flip-flop and the AND gate comprising a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer;
- wherein the first transistor and the second transistor are electrically connected to each other,
- wherein the second transistor comprises an oxide semiconductor layer including a channel formation region, and
- wherein the oxide semiconductor layer comprises crystals whose c-axis is in direction perpendicular to a surface of the oxide semiconductor layer.
A semiconductor device comprising:
- a flip-flop and a NOR gate electrically connected to each other, at least one of the flip-flop and the NOR gate comprising a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer;
- wherein the first transistor and the second transistor are electrically connected to each other,
- wherein the second transistor comprises an oxide semiconductor layer including a channel formation region, and
- wherein the oxide semiconductor layer comprises crystals whose c-axis is in direction perpendicular to a surface of the oxide semiconductor layer.
A semiconductor device comprising:
- a flip-flop and a latch electrically connected to each other, at least one of the flip-flop and the latch comprising a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer;
- wherein the first transistor and the second transistor are electrically connected to each other,
- wherein the second transistor comprises an oxide semiconductor layer including a channel formation region, and
- wherein the oxide semiconductor layer comprises crystals whose c-axis is in direction perpendicular to a surface of the oxide semiconductor layer.
Dependencies are inferred from the claim text.