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US 8,570,069 B2Granted
Clock gating cell circuit
AssigneeSTMicroelectronics S.r.l.
InventorsMounir Zid, Alberto Scandurra
Life of this patent
Estimating the term…
Abstract
A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output.
Claims22
A circuit comprising:
- a first Muller gate having a first input configured to receive a clock signal, a second input configured to receive an enable signal and a first output;
- a delay circuit configured to delay the clock signal by a delay based on a propagation delay associated with the first Muller gate to produce a first delayed clock signal;
- a second Muller gate having a first input configured to receive the first output of the first Muller gate and a second input configured to receive the first delayed clock signal from said delay circuit;
- and
- a logic circuit having a first input configured to receive a second delayed clock signal from said delay circuit, a second input configured to receive an input dependent on an output of the second Muller gate, and an output configured to provide a gated clock output.
2 more elements
A circuit comprising:
- a first Muller gate having a first input configured to receive a clock signal, a second input configured to receive an enable signal and a first output;
- a first delay circuit configured to delay the clock signal by a delay equal to a propagation delay associated with the first Muller gate to produce a first delayed clock signal;
- a second Muller gate having a first input configured to receive the first output of the first Muller and a second input configured to receive the first delayed clock signal from said first delay circuit;
- a second delay circuit configured to delay the first delayed clock signal from said first delay circuit to produce a second delayed clock signal;
- and
- a logic circuit having a first input configured to receive the second delayed clock signal from said second delay circuit, a second input configured to receive an output from said second Muller gate, and an output configured to provide a gated clock output.
3 more elements
A circuit comprising:
- a first Muller gate configured to receive a clock signal and an enable signal and produce a first output;
- a first delay circuit configured to delay the clock signal by a propagation delay associated with the first Muller gate to produce a first delayed clock signal;
- a second Muller gate configured to receive the first output of the first Muller gate and the first delayed clock signal from the first delay circuit;
- a second delay circuit, connected in series to the first delay circuit, the second delay circuit configured to delay the first delayed clock signal by a second propagation delay associated with the second Muller gate to produce a second delayed clock signal;
- and
- a logic circuit configured to produce a gated clock output based on receiving the second delayed clock signal and an output of the second Muller gate.
3 more elements
Dependencies are inferred from the claim text.