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US 8,570,068 B2Granted
Circuit for reducing negative bias temperature instability
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
Life of this patent
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Abstract
A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.
Claims20
A circuit, comprising:
- an operational PMOS transistor of a logic gate driver;
- a control circuit configured to turn off the operational PMOS transistor during a standby mode;
- a first PMOS transistor;
- and
- an output node;
- wherein the operational PMOS transistor is coupled to the output node and the first PMOS transistor is configured to keep the output node at a logical 1 during the standby mode, and a gate of the first PMOS transistor is coupled to an output of an inverter and a drain of the first PMOS transistor is coupled to an input of the inverter, the control circuit includes a second PMOS transistor coupled to the operational PMOS transistor for turning off the operational PMOS transistor during a standby mode, and the second PMOS is outside a signal path of a clock signal.
3 more elements
A method, comprising:
- turning off an operational PMOS transistor of a logic gate driver by a control circuit during a standby mode, wherein turning off the operational PMOS transistor comprises processing a standby signal and a clock signal through a first NOR gate;
- and
- keeping an output node at a logical 1 during the standby mode by a first PMOS transistor coupled to the output node.
A circuit, comprising:
- an operational PMOS transistor of a logic gate driver;
- a control circuit configured to turn off the operational PMOS transistor during a standby mode;
- a first PMOS transistor configured to receive a standby signal,
- an output node coupled to the operational PMOS transistor;
- and
- an NMOS transistor that is coupled to the operational PMOS transistor and the output node,
- wherein the standby signal and a clock signal are coupled to the control circuit, and the first PMOS transistor is configured to keep the output node at a logical 1 during the standby mode, and a gate of the operational PMOS transistor is coupled to a first NOR gate, and a gate of the NMOS transistor is coupled to a second NOR gate separate from the first NOR gate.
4 more elements
Dependencies are inferred from the claim text.