# US 8,570,064 B1 · Methods and systems for programmable implementation of on-chip termination calibration > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,064 B1 - Document ID: US8570064B1 - Status: Granted - Kind: B1 - Application number: 13/294,741 - Filed: 2011-11-11 - Granted: 2013-10-29 - Earliest claimed: 2011-11-11 - Assignees: Altera Corporation - Applicants: Foong Tek Chan; Ket Chiew Sia - Inventors: Foong Tek Chan; Ket Chiew Sia - Web page: https://patentgrep.com/patent/US8570064B1 ## CPC - H03K 19/018578: {with at least one differential stage} - H03K 19/0005: {Modifications of input or output impedance} - H03K 19/018585: {programmable} - H04L 25/0278: {Arrangements for impedance matching} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Methods, circuits, and systems for termination calibration are provided. Differential input buffer circuitry is used to compare a signal level at an input/output pad and a first reference signal level. Control circuitry is used to control a controllably variable impedance based on the output of the differential input buffer circuitry. Optionally, second differential input buffer circuitry is used to compare the signal level at the input/output pad to a second reference signal level. The control circuitry is used to control the controllably variable impedance based on the output of both the first and the second differential input buffer circuitry. ## Claims ### Claim 1 A system comprising: first differential input buffer circuitry configured to output a first input buffer circuitry output signal by comparing a first signal level at an input/output pad with a second signal level; termination circuitry configured to provide a controllably variable impedance associated with the input/output pad; control circuitry configured to control the controllably variable impedance provided by the termination circuitry based at least in part on a voltage level of the first differential input buffer circuitry output signal; and second differential input buffer circuitry configured to output a second differential input buffer circuitry output signal by comparing the first signal level associated with the input/output pad with a third signal level, wherein: the third signal level is different from the second signal level, the control circuitry is further configured to control the impedance provided by the termination circuitry based at least in part on the second differential input buffer circuitry output signal, the first differential input buffer circuitry comprises high speed transceiver logic (HSTL) circuitry, and the second differential input buffer circuitry comprises low voltage differential buffer (LVDS) circuitry. ### Claim 2 (depends on 1) The system of claim 1, wherein the first differential input buffer circuitry and the second differential input buffer circuitry are contained within a first input/output bank of a larger system. ### Claim 3 (depends on 1) The system of claim 1 wherein: the first differential input buffer circuitry is contained within a first input/output bank of a larger system, and the second differential input buffer circuitry is contained within a second input/output bank of the larger system. ### Claim 4 (depends on 1) The system of claim 1, wherein the control circuitry is further configured to transmit and receive data based at least in part on controlling the controllably variable impedance provided by the termination circuitry. ### Claim 5 (depends on 1) The system of claim 1, wherein the control circuitry is configured to control the controllably variable impedance provided by the termination circuitry to match an impedance of a transmission path, wherein: the transmission path is coupled to the input/output pad. ### Claim 6 (depends on 1) The system of claim 1, wherein the control circuitry comprises programmable logic circuitry. ### Claim 7 (depends on 6) The system of claim 6, wherein: the programmable logic circuitry is configured to control the controllably variable impedance provided by the termination circuitry according to calibration instructions implemented in soft logic. ### Claim 8 (depends on 1) The system of claim 1, wherein the termination circuitry comprises a plurality of transistors. ### Claim 9 (depends on 1) The system of claim 1, wherein the first differential input buffer circuitry is part of differential signaling circuitry. ### Claim 10 A system comprising: a first input/output pad; a second input/output pad; input/output circuitry comprising: a first differential input buffer circuitry, wherein: a first input of the first differential input buffer circuitry is coupled to the first input/output pad, and a second input of the first differential input buffer circuitry is coupled to the second input/output pad; and second differential input buffer circuitry, wherein: a first input of the second differential input buffer circuitry is coupled to the first input/output pad, and a second input of the second differential input buffer circuitry is coupled a reference voltage level; and control circuitry configured to control a controllably variable impedance provided by a termination circuitry based at least in part on an output voltage level of the first differential input buffer circuitry and based at least in part on an output voltage level of the second differential input buffer circuitry. ### Claim 11 (depends on 10) The system of claim 10, wherein the control circuitry is a programmable logic circuitry. ### Claim 12 (depends on 11) The system of claim 11, wherein: the control circuitry is configured to control the controllably variable impedance provided by the termination circuitry according to calibration instructions implemented in soft logic. ### Claim 13 (depends on 10) The system of claim 10, wherein the control circuitry is further configured to transmit and receive data based at least in part on controlling the controllably variable impedance provided by the termination circuitry. ### Claim 14 (depends on 10) The system of claim 10, wherein the control circuitry is further configured to control the controllably variable impedance provided by the termination circuitry to match an impedance of a transmission path, wherein: the transmission path is coupled to the first input/output pad. ### Claim 15 A method for using a circuit, the method comprising: providing first differential input buffer circuitry output signal by comparing, with first differential input buffer circuitry, a first signal level associated with an input/output pad with a second signal level; controlling the impedance associated with the input/output pad based at least in part on a voltage level of the first differential input buffer circuitry output signal; and providing second differential input buffer circuitry configured to output a second differential input buffer circuitry output signal by comparing the first signal level associated with the input/output pad with a third signal level, wherein: the third signal level is different from the second signal level, the control circuitry is further configured to control the impedance provided by the termination circuitry based at least in part on the second differential input buffer circuitry output signal, the first differential input buffer circuitry comprises high speed transceiver logic (HSTL) circuitry, and the second differential input buffer circuitry comprises low voltage differential buffer (LVDS) circuitry. ### Claim 16 (depends on 15) The method of claim 15, wherein the first buffer circuitry is part of differential signaling circuitry. ### Claim 17 (depends on 15) The method of claim 15, wherein the controlling the impedance comprises matching the impedance of the input/output pad to an impedance of a transmission path, wherein coupled to the input/output pad. ### Claim 18 (depends on 15) The method of claim 15, further comprising transmitting and receiving data based at least in part on controlling the impedance associated with the input/output pad.