# US 8,570,061 B2 · (N-1)-out-of-N voter mux with enhanced drive > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,061 B2 - Document ID: US8570061B2 - Status: Granted - Kind: B2 - Application number: 13/176,405 - Filed: 2011-07-05 - Published: 2013-01-10 - Granted: 2013-10-29 - Earliest claimed: 2011-07-05 - Assignees: Honeywell International Inc. - Applicants: Keith Golke - Inventors: Keith Golke - Web page: https://patentgrep.com/patent/US8570061B2 ## CPC - H03K 19/00338: {In field effect transistor circuits} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N−1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths. ## Claims ### Claim 1 A circuit comprising: a plurality of inputs; an output; a high voltage source; a low voltage source; a first plurality of logic paths connecting the output to the high voltage, wherein each logic path of the first plurality of logic paths comprises two transistors, wherein in response to a majority but not all of the plurality of inputs having a same value, two or more logic paths of the first plurality of logic paths enable current flow between the high voltage source and the output; a second plurality of logic paths connecting the output to the low voltage, wherein each logic path of the second plurality of logic paths comprises two transistors, wherein a first logic path of the second plurality of logic paths comprises a first re-channel MOSFET and a second n-channel MOSFET, and wherein a second logic path of the second plurality of logic paths comprises the second n-channel MOSFET and a third n-channel MOSFET, and wherein a source of the first n-channel MOSFET is connected to the low voltage source and a source of the third n-channel is connected to the low voltage source; a drain of the first n-channel MOSFET is connected to a source of the second n-channel MOSFET and a drain of the third n-channel MOSFET is connected to the source of the second n-channel MOSFET; and, a drain of the second n-channel MOSFET is connected to the output. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the two transistors of each logic path of the first plurality of logic paths are p-channel metal-oxide semiconductor field-effect transistors (MOSFETs). ### Claim 3 (depends on 2) The circuit of claim 2, wherein each path comprises a first p-channel MOSFET connected to the high voltage source and a second p-channel MOSFET connected between the first p-channel and the output. ### Claim 4 (depends on 3) The circuit of claim 3, wherein the first p-channel MOSFET has a larger gate width than the second p-channel MOSFET. ### Claim 5 (depends on 1) The circuit of claim 1, wherein the first n-channel MOSFET has a larger gate width than the second n-channel MOSFET. ### Claim 6 (depends on 1) The circuit of claim 1, wherein each input is connected to a gate of a MOSFET from the first plurality of MOSFETs and a gate of a MOSFET from the second plurality of MOSFETs; wherein each MOSFET of the first plurality of MOSFETs is configured to allow current from a source of the MOSFET of the first plurality to a drain of the MOSFET of the plurality in response to a low voltage being applied to the gate of the MOSFET of the first plurality and to inhibit current flow from the drain of the MOSFET of the first plurality to the source of the MOSFET of the first plurality in response to a high voltage being applied to the gate of the MOSFET of the plurality; wherein each MOSFET of the second plurality of MOSFETs is configured to inhibit current from a source of the MOSFET of the second plurality to a drain of the MOSFET of the second plurality in response to a low voltage being applied to the gate of the MOSFET of the second plurality and to allow current flow from the drain of the MOSFET of the second plurality to the source of MOSFET of the second plurality in response to a high voltage being applied to the gate of the MOSFET of the second plurality. ### Claim 7 (depends on 1) The circuit of claim 1, wherein the first plurality of MOSFETs inhibits current flow through all paths of the first plurality of paths when one input of the plurality of inputs is low and the other inputs of the plurality of inputs are high. ### Claim 8 (depends on 1) The circuit of claim 1, wherein the second plurality of MOSFETs inhibits current flow through all paths of the second plurality of paths when one input of the plurality of inputs is high and the other inputs of the plurality of inputs are low. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the first plurality of MOSFETs enables current flow through a subset of the first plurality of paths when one input of the plurality of inputs is high and the other inputs of the plurality of inputs are low. ### Claim 10 (depends on 1) The circuit of claim 1, wherein the second plurality of MOSFETs enables current flow through a subset of the second plurality of paths when one input of the plurality of inputs is low and the other inputs of the plurality of inputs are high. ### Claim 11 (depends on 1) The circuit of claim 1, wherein the circuit is a 2-out-of-3 voting circuit. ### Claim 12 (depends on 1) The circuit of claim 1, wherein the circuit is a 3-out-of-4 voting circuit. ### Claim 13 (depends on 1) The circuit of claim 1, wherein the circuit is an (N−1)-out-of-N voting circuit. ### Claim 14 A 2-out-of-3 voting circuit comprising: a first input; a second input; a third input; a high voltage source; a low voltage source; a first p-channel metal-oxide silicon field-effect transistor (MOSFET), wherein a source of the first p-channel MOSFET is connected to the high voltage source and a gate of the first p-channel MOSFET is connected to the first input; a second p-channel MOSFET, wherein a source of the second p-channel MOSFET is connected to the high voltage source and a gate of the second p-channel MOSFET is connected to the third input; a third p-channel MOSFET, wherein a source of the third p-channel MOSFET is connected to the high voltage source and a gate of the third p-channel MOSFET is connected to the second input; a fourth p-channel MOSFET, wherein a source of the fourth p-channel MOSFET is connected to the high voltage source and a gate of the fourth p-channel MOSFET is connected to the first input; a fifth p-channel MOSFET, wherein a source of the fifth p-channel MOSFET is connected to the high voltage source and a gate of the fifth p-channel MOSFET is connected to the third input; a sixth p-channel MOSFET, wherein a source of the sixth p-channel MOSFET is connected to the high voltage source and a gate of the sixth p-channel MOSFET is connected to the second input; a first n-channel MOSFET, wherein a source of the first n-channel MOSFET is connected to the low voltage source and a gate of the first n-channel MOSFET is connected to the first input; a second n-channel MOSFET, wherein a source of the second n-channel MOSFET is connected to the low voltage source and a gate of the second n-channel MOSFET is connected to the third input; a third n-channel MOSFET, wherein a source of the third n-channel MOSFET is connected to the low voltage source and a gate of the third n-channel MOSFET is connected to the second input; a fourth n-channel MOSFET, wherein a source of the fourth n-channel MOSFET is connected to the low voltage source and a gate of the fourth n-channel MOSFET is connected to the first input; a fifth n-channel MOSFET, wherein a source of the fifth n-channel MOSFET is connected to the low voltage source and a gate of the fifth n-channel MOSFET is connected to the third input; a sixth n-channel MOSFET, wherein a source of the sixth n-channel MOSFET is connected to the low voltage source and a gate of the sixth n-channel MOSFET is connected to the second input; a seventh p-channel MOSFET, wherein a source of the seventh p-channel MOSFET is connected to a drain of the first p-channel MOSFET and a drain of the second p-channel MOSFET and a gate of the seventh p-channel MOSFET is connected to the second input; an eighth p-channel MOSFET, wherein a source of the eighth p-channel MOSFET is connected to a drain of the third p-channel MOSFET and a drain of the fourth p-channel MOSFET, and a gate of the eighth p-channel MOSFET is connected to the third input; a ninth p-channel MOSFET, wherein a source of the ninth p-channel MOSFET is connected to a drain of the fifth p-channel MOSFET and a drain of the sixth p-channel MOSFET, and a gate of the ninth p-channel MOSFET is connected to the first input; a seventh n-channel MOSFET, wherein a source of the seventh n-channel MOSFET is connected to a drain of the first n-channel MOSFET and a drain of the second n-channel MOSFET, and a gate of the seventh n-channel MOSFET is connected to the second input; an eighth n-channel MOSFET, wherein a source of the eighth n-channel MOSFET is connected to a drain of the third n-channel MOSFET and a drain of the fourth n-channel MOSFET, and a gate of the eighth n-channel MOSFET is connected to the third input; a ninth n-channel MOSFET, wherein a source of the ninth n-channel MOSFET is connected to a drain of the fifth n-channel MOSFET and a drain of the sixth n-channel MOSFET, and a gate of the ninth n-channel MOSFET is connected to the first input; an output, wherein the output is connected to a drain of the seventh n-channel MOSFET, a drain of the eighth n-channel MOSFET, a drain of the ninth n-channel MOSFET, a drain of the seventh p-channel MOSFET, a drain of the eighth p-channel MOSFET, and a drain of the ninth p-channel MOSFET. ### Claim 15 A 3-out-of-4 voting circuit comprising: a first input; a second input; a third input; a fourth input; a high voltage source; a low voltage source; a first p-channel metal-oxide silicon field-effect transistor (MOSFET), wherein a source of the first p-channel MOSFET is connected to the high voltage source and a gate of the first p-channel MOSFET is connected to the first input; a second p-channel MOSFET, wherein a source of the second p-channel MOSFET is connected to the high voltage source and a gate of the second p-channel MOSFET is connected to the second input; a third p-channel MOSFET, wherein a source of the third p-channel MOSFET is connected to a drain of the first p-channel MOSFET and a drain of the second p-channel MOSFET, and a gate of the third p-channel MOSFET is connected to the third input; a fourth p-channel MOSFET, wherein a source of the fourth p-channel MOSFET is connected to a drain of the first p-channel MOSFET and a drain of the second p-channel MOSFET, and a gate of the fourth p-channel MOSFET is connected to the fourth input; a first n-channel MOSFET, wherein a source of the first n-channel MOSFET is connected to the low voltage source and a gate of the first n-channel MOSFET is connected to the first input; a second n-channel MOSFET, wherein a source of the second n-channel MOSFET is connected to the low voltage source and a gate of the second n-channel MOSFET is connected to the second input; a third n-channel MOSFET, wherein a source of the third n-channel MOSFET is connected to a drain of the first n-channel MOSFET and a drain of the second n-channel MOSFET, and a gate of the third n-channel MOSFET is connected to the third input; a fourth n-channel MOSFET, wherein a source of the fourth n-channel MOSFET is connected to a drain of the first n-channel MOSFET and a drain of the second n-channel MOSFET, and a gate of the fourth n-channel MOSFET is connected to the fourth input; an output, wherein the output is connected to a drain of the third n-channel MOSFET, a drain of the fourth n-channel MOSFET, a drain of the third p-channel MOSFET, a drain of the fourth p-channel MOSFET.