# US 8,570,056 B2 · Semiconductor inspection apparatus, semiconductor wafer positioning method, and semiconductor wafer inspection method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,056 B2 - Document ID: US8570056B2 - Status: Granted - Kind: B2 - Application number: 12/866,223 - Filed: 2009-02-26 - Published: 2010-12-23 - Granted: 2013-10-29 - Earliest claimed: 2008-02-28 - Assignees: NEC Corporation - Applicants: Yoshio Kameda; Masamoto Tago; Yoshihiro Nakagawa; Koichiro Noguchi - Inventors: Yoshio Kameda; Masamoto Tago; Yoshihiro Nakagawa; Koichiro Noguchi - Web page: https://patentgrep.com/patent/US8570056B2 ## CPC - G01R 31/2891: {related to sensing or controlling of force, position, temperature (G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05)} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A semiconductor inspection apparatus comprising: a plurality of wafer stages, provided independently for each of a plurality of laminated semiconductor wafers, that directly or indirectly secure the corresponding semiconductor wafers and that possess a mechanism for positioning the corresponding semiconductor wafers; and a probe card, arranged outside or in between the plurality of laminated semiconductor wafers so as to face the semiconductor wafers, that transmits a signal or power to the plurality of semiconductor wafers. ## Claims ### Claim 1 A semiconductor inspection apparatus comprising: a plurality of wafer stages, provided independently for each of a plurality of laminated semiconductor wafers, that directly or indirect secure said corresponding semiconductor wafers and that possess a mechanism for positioning said corresponding semiconductor wafers; and a probe card, arranged outside or in between said plurality of laminated semiconductor wafers so as to face said semiconductor wafers, that transmits a signal or power to said plurality of semiconductor wafers, wherein a plurality of subject chips are formed in said semiconductor wafers; and said probe card comprises one or more inspecting chips capable of performing non-contact transmission to said subject chips in said semiconductor wafers, wherein said subject chip includes at least one non-contact transmission electrode that performs non-contact transmission of a signal or power, and said inspecting chip includes at least one non-contact transmission electrode that performs non-contact transmission of a signal or power to said non-contact transmission electrode of said subject chip. ### Claim 2 (depends on 1) The semiconductor inspection apparatus as defined in claim 1, wherein said non-contact transmission electrode is a communication coil. ### Claim 3 (depends on 1) The semiconductor inspection apparatus as defined in claim 1, comprising: a sheet to which a predetermined semiconductor wafer of said semiconductor wafers is detachably adhered; wherein a predetermined wafer stage of said wafer stages is able to secure said sheet thereon. ### Claim 4 (depends on 3) The semiconductor inspection apparatus as defined in claim 3, wherein said sheet is a dicing sheet. ### Claim 5 (depends on 3) The semiconductor inspection apparatus as defined in claim 3, wherein a predetermined wafer stage of said wafer stages is able to secure said sheet thereon by suction. ### Claim 6 (depends on 1) The semiconductor inspection apparatus as defined in claim 1, wherein said plurality of wafer stages of said semiconductor inspection apparatus are fixed on a common base; and said probe card is embedded in said wafer stage that secures said semiconductor wafer closest to said base. ### Claim 7 (depends on 1) The semiconductor inspection apparatus as defined in claim 1, wherein said plurality of wafer stages of said semiconductor inspection apparatus are fixed on a common base; and said probe card is disposed inside said wafer stage that secures said semiconductor wafer closest to said base. ### Claim 8 (depends on 1) The semiconductor inspection apparatus as defined in claim 1, wherein said plurality of wafer stages of said semiconductor inspection apparatus are fixed on a common base; and said wafer stage that supports one of said semiconductor wafers on the side of said base out of two adjacent semiconductor wafers of said plurality of semiconductor wafers of said semiconductor inspection apparatus is disposed inside said wafer stage that supports said other semiconductor wafer. ### Claim 9 (depends on 3) The semiconductor inspection apparatus as defined in claim 3, wherein said semiconductor wafer has a wafer electrode electrically connected to each of said subject chips in a region where said subject chip is not disposed; and said sheet has a sheet electrode that contacts said wafer electrode at a position where said sheet electrode faces said wafer electrode. ### Claim 10 A semiconductor inspection apparatus, comprising: a plurality of wafer stages, provided independently for each of a plurality of laminated semiconductor wafers, that directly or indirectly secure said corresponding semiconductor wafers and that possess a mechanism for positioning said corresponding semiconductor wafers; a probe card, arranged outside or in between said plurality of laminated semiconductor wafers so as to face said semiconductor wafers, that transmits a signal or power to said plurality of semiconductor wafers; wherein said semiconductor wafer has a wafer electrode electrically connected to each of subject chips in a region where said subject chip is not disposed; a sheet having a sheet electrode that contacts said wafer electrode at a position where said sheet electrode faces said wafer electrode; and a pressing member that presses said wafer electrode of said semiconductor wafer, which is furthest from said base and said sheet electrode contacting said wafer electrode of said semiconductor wafer furthest from said base to the side of said base. ### Claim 11 (depends on 1) The semiconductor inspection apparatus as defined in claim 1, comprising: an insulating sheet interposed between said probe card and said semiconductor wafer facing each other. ### Claim 12 (depends on 11) The semiconductor inspection apparatus as defined in claim 11, wherein said semiconductor wafer has a wafer electrode electrically connected to each of said subject chips in a region where said subject chip is not disposed; and said insulating sheet has a sheet electrode that contacts said wafer electrode at a position where said sheet electrode faces said wafer electrode. ### Claim 13 (depends on 1) The semiconductor inspection apparatus as defined in claim 1, wherein each of said semiconductor wafers is of the same type as each other. ### Claim 14 A semiconductor wafer positioning method, comprising: positioning a plurality of semiconductor wafers laminated with each other and secured by each of a plurality of wafer stages independently capable of positioning relative to a probe card provided outside or in between said plurality of semiconductor wafers so as to face said semiconductor wafers for each of said semiconductor wafers; wherein said positioning is performed based on non-contact transmission electrodes provided in each of said plurality of semiconductor wafers and in said probe card. ### Claim 15 A semiconductor wafer inspection method, comprising: (a) positioning a plurality of semiconductor wafers laminated with each other and secured by each of a plurality of wafer stages independently capable of positioning and a probe card provided outside or in between said plurality of semiconductor wafers so as to face said semiconductor wafers for each of the semiconductor wafers termed as “step (a)”; (b) having said probe card simultaneously transmit an inspection signal to subject chips provided in each of said semiconductor wafers (termed as “step (b)”); and (c) having each of said subject chips that have received said inspection signal simultaneously transmit the respective inspection result to said probe card (termed as “step (c)”); wherein a plurality of subject chips are formed in said semiconductor wafers; said probe card comprises one or more inspecting chips capable of performing non-contact transmission to said subject chips in said semiconductor wafers; said subject chip includes at least one non-contact transmission electrode that performs non-contact transmission of a signal or power; and said inspecting chip includes at least one non-contact transmission electrode that performs non-contact transmission of a signal or power to said non-contact transmission electrode of said subject chip; and said step (b) and said step (c) are performed with non-contact transmission between an inspecting chip provided in said probe card and said subject chips. ### Claim 16 A semiconductor apparatus manufacturing method, comprising: positioning a plurality of semiconductor wafers laminated with each other and secured by each of a plurality of wafer stages independently capable of positioning relative to a probe card provided outside or in between said plurality of semiconductor wafers so as to face said semiconductor wafers for each of said semiconductor wafers; wherein said positioning is performed based on non-contact transmission electrodes provided in each of said plurality of semiconductor wafers and in said probe card.