# US 8,570,052 B1 · Methods and circuits for measuring mutual and self capacitance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,052 B1 - Document ID: US8570052B1 - Status: Granted - Kind: B1 - Application number: 13/664,421 - Filed: 2012-10-31 - Granted: 2013-10-29 - Earliest claimed: 2008-02-27 - Assignees: Cypress Semiconductor Corporation - Applicants: Cypress Semiconductor Corporation - Inventors: Andriy Mahartya - Web page: https://patentgrep.com/patent/US8570052B1 ## CPC - G01R 27/2605: {Measuring capacitance (capacitive sensors G01D5/24)} - H03K 17/962: {Capacitive touch switches} - H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) - H03K 2217/960725: Charge-transfer - H03K 2217/960775: Emitter-receiver or "fringe" type detection, i.e. one or more field emitting electrodes and corresponding one or more receiving electrodes - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An embodiment of a capacitance measurement circuit may include multiple switches, a first node coupled with a first electrode and coupled with at least a first switch of the multiple switches, and a second node coupled with a second electrode and coupled with at least a second switch of the multiple switches, where the multiple switches are configured to reduce an influence of a self-capacitance of the first electrode and a self-capacitance of the second electrode on an output signal during measurement of a mutual capacitance between the first electrode and the second electrode, and where the multiple switches are configured to reduce an influence of the mutual capacitance on the output signal during measurement of at least one of the self-capacitance of the first electrode and the self-capacitance of the second electrode. ## Claims ### Claim 1 A capacitance measurement circuit, comprising: a plurality of switches; a first node coupled with a first electrode and coupled with at least a first switch of the plurality of switches; and a second node coupled with a second electrode and coupled with at least a second switch of the plurality of switches, wherein the plurality of switches is configured to reduce an influence of a self-capacitance of the first electrode and a self-capacitance of the second electrode on an output signal during measurement of a mutual capacitance between the first electrode and the second electrode, and wherein the plurality of switches is configured to reduce an influence of the mutual capacitance on the output signal during measurement of at least one of the self-capacitance of the first electrode and the self-capacitance of the second electrode. ### Claim 2 (depends on 1) The capacitance measurement circuit of claim 1, further comprising an integration capacitor coupled with at least one of the plurality of switches, wherein the plurality of switches is further configured to transfer charge to the integration capacitor from at least one of the first electrode and the second electrode. ### Claim 3 (depends on 2) The capacitance measurement circuit of claim 2, wherein the plurality of switches is configured to reduce the influence of the self-capacitances by minimizing a potential difference between each of the first node and the second node and a terminal of the integration capacitor during at least one switching phase of the plurality of switches. ### Claim 4 (depends on 2) The capacitance measurement circuit of claim 2, wherein the plurality of switches is configured to reduce the influence of the mutual capacitance by applying a potential difference across the first electrode and the second electrode that is approximately equal to another potential difference between terminals of the integration capacitor during at least one switching phase of the plurality of switches. ### Claim 5 (depends on 1) The capacitance measurement circuit of claim 1, wherein the first node is coupled with a third switch of the plurality of switches and the second node is coupled with a fourth switch of the plurality of switches. ### Claim 6 (depends on 5) The capacitance measurement circuit of claim 5, wherein the first switch and the second switch are closed simultaneously, and wherein the third switch and the fourth switch are closed simultaneously according to a first switching sequence for operating the plurality of switches during the measurement of the at least one self-capacitance. ### Claim 7 (depends on 5) The capacitance measurement circuit of claim 5, wherein the first switch and the fourth switch are closed simultaneously, and wherein the second switch and the third switch are closed simultaneously according to a second switching sequence for operating the plurality of switches during the measurement of the mutual capacitance. ### Claim 8 A capacitance measurement circuit, comprising: a first node coupled with a first electrode; a second node coupled with a second electrode capacitively coupled with the first electrode; and a plurality of switches coupled with the first node and the second node and configured to reduce an influence of a mutual capacitance on an output signal by operating according to a first switching sequence during measurement of a self-capacitance for at least one of the first electrode and the second electrode, and configured to reduce an influence of the self-capacitance of the first electrode and the self-capacitance of the second electrode on the output signal by operating according to a second switching sequence different from the first sequence during measurement of the mutual capacitance between the first electrode and the second electrode. ### Claim 9 (depends on 8) The capacitance measurement circuit of claim 8, further comprising an output node coupled with at least one of the plurality of switches and configured to output the output signal based on a current generated by operation of the plurality of switches. ### Claim 10 (depends on 8) The capacitance measurement circuit of claim 8, further comprising an integration capacitor coupled with at least one of the plurality of switches, wherein the plurality of switches is further configured to transfer charge to the integration capacitor from at least one of the first electrode and the second electrode. ### Claim 11 (depends on 10) The capacitance measurement circuit of claim 10, wherein the plurality of switches is configured to reduce the influence of the mutual capacitance when operating according to the first switching sequence by applying a potential difference between the first electrode and the second electrode that is approximately equal to another potential difference between terminals of the integration capacitor during at least one switching phase of the plurality of switches. ### Claim 12 (depends on 10) The capacitance measurement circuit of claim 10, wherein the plurality of switches is configured to reduce the influence of the self-capacitances when operating according to the second switching sequence by minimizing a potential difference between each of the first node and the second node and a terminal of the integration capacitor during at least one switching phase of the plurality of switches. ### Claim 13 (depends on 8) The capacitance measurement circuit of claim 8, wherein the plurality of switches further comprises a third switch coupled with the first node and a fourth switch coupled with the second node, and wherein the first switch and the second switch are closed simultaneously, and wherein the third switch and the fourth switch are closed simultaneously according to a first switching sequence for operating the plurality of switches during the measurement of the at least one self-capacitance. ### Claim 14 (depends on 8) The capacitance measurement circuit of claim 8, wherein the plurality of switches further comprises a third switch coupled with the first node and a fourth switch coupled with the second node, and wherein the first switch and the fourth switch are closed simultaneously, and wherein the second switch and the third switch are closed simultaneously according to a second switching sequence for operating the plurality of switches during the measurement of the mutual capacitance. ### Claim 15 A method, comprising: operating a plurality of switches according to a first switching sequence to reduce an influence of a mutual capacitance between a pair of electrodes for a period of time during which a self-capacitance is measured for at least one of the pair of electrodes; and operating the plurality of switches according to a second switching sequence to reduce an influence of self-capacitances for each of the pair of electrodes for a period of time during which the mutual capacitance between the pair of electrodes is measured. ### Claim 16 (depends on 15) The method of claim 15, further comprising storing charge generated by operation of the plurality of switches according to the first switching sequence and the second switching sequence in an integration capacitor coupled with at least one of the plurality of switches. ### Claim 17 (depends on 16) The method of claim 16, wherein minimizing the influence of the self-capacitances further comprises minimizing a potential difference between each of the pair of electrodes and a terminal of the integration capacitor during at least one switching phase of the plurality of switches. ### Claim 18 (depends on 16) The method of claim 16, wherein minimizing the influence of the mutual capacitance further comprises applying a potential difference between the first electrode and the second electrode that is approximately equal to another potential difference between terminals of the integration capacitor during at least one switching phase of the plurality of switches. ### Claim 19 (depends on 15) The method of claim 15, wherein operating the plurality of switches according to the first switching sequence further comprises: closing a first switch and a second switch of the plurality of switches while a third switch and a fourth switch of the plurality of switches remain open; and closing the third switch and the fourth switch, while the first switch and the second switch remain open. ### Claim 20 (depends on 15) The method of claim 15, wherein operating the plurality of switches according to the second switching sequence further comprises: closing a first switch and a fourth switch of the plurality of switches while a second switch and a third switch of the plurality of switches remain open; and closing the second switch and the third switch while the first switch and the fourth switch remain open.