# US 8,570,016 B1 · Duty cycle generator and power converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,016 B1 - Document ID: US8570016B1 - Status: Granted - Kind: B1 - Application number: 13/586,849 - Filed: 2012-08-15 - Published: 2013-10-24 - Granted: 2013-10-29 - Earliest claimed: 2012-04-19 - Assignees: Anpec Electronics Corporation - Applicants: Yueh-Lung Kuo; Chih-Yuan Chen - Inventors: Yueh-Lung Kuo; Chih-Yuan Chen - Web page: https://patentgrep.com/patent/US8570016B1 ## CPC - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - H02M 1/44: Circuits or arrangements for compensating for electromagnetic interference in converters or inverters - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - H02M 3/1588: {comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence)} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract A duty cycle generator for generating a duty cycle signal to a power converter is disclosed. The duty cycle generator includes a first inverter, a second inverter, a signal protection unit including an input terminal coupled to the duty cycle signal for generating a break pulse to generate a protected duty cycle signal, a comparator for comparing a triangle-wave signal with a comparison signal to generate a comparison result, a NOR gate for generating a reset signal according to the comparison result and the protected duty cycle signal, an SR-latch for outputting a turn-on signal according to the clock signal and the reset signal, and an AND gate for generating the duty cycle signal according to the inverted clock signal and the turn-on signal. ## Claims ### Claim 1 A duty cycle generator for generating a duty cycle signal to a power converter, comprising: a first inverter coupled to a clock signal for inverting the clock signal; a second inverter cascaded to the first inverter for outputting the clock signal; a signal protection unit including an input terminal coupled to the duty cycle signal for generating a break pulse to generate a protected duty cycle signal; a comparator including a positive input terminal coupled to a comparison signal of the power converter and a negative input terminal coupled to a triangle-wave signal for comparing the triangle-wave signal with the comparison signal to generate a comparison result; a NOR gate including a first input terminal coupled to the comparison result, and a second input terminal coupled to an output terminal of the signal protection unit for generating a reset signal according to the comparison result and the protected duty cycle signal; an SR-latch including a set input terminal coupled to an output terminal of the second inverter, a reset input terminal coupled to an output terminal of the NOR gate, and an output terminal for outputting a turn-on signal according to the clock signal and the reset signal; and an AND gate including a first input terminal coupled to the output terminal of the SR-latch, and a second input terminal coupled to the output terminal of the first inverter and the input terminal of the second inverter for generating the duty cycle signal according to the inverted clock signal and the turn-on signal. ### Claim 2 (depends on 1) The duty cycle generator of claim 1, further comprising a triangle-wave generator for generating the triangle-wave signal. ### Claim 3 (depends on 1) The duty cycle generator of claim 1, wherein when the comparison signal is greater than the triangle-wave signal and the clock signal is at a high voltage, the duty cycle signal outputted by the AND gate is at a low voltage. ### Claim 4 (depends on 3) The duty cycle generator of claim 3, wherein when the comparison signal is greater than the triangle-wave signal and the clock signal is at a low voltage, the duty cycle signal outputted by the AND gate is at a high voltage. ### Claim 5 (depends on 4) The duty cycle generator of claim 4, wherein when the comparison signal is greater than the triangle-wave signal and the clock signal is at a low voltage, the break pulse is at a high voltage. ### Claim 6 (depends on 1) The duty cycle generator of claim 1, wherein a pulse width of the break pulse is less than a pulse width of the duty cycle signal. ### Claim 7 (depends on 1) The duty cycle generator of claim 1, wherein the power converter is a voltage mode power converter. ### Claim 8 A power converter for converting an input voltage to an output voltage, comprising: a duty cycle generator for generating a duty cycle signal, comprising: a first inverter coupled to a clock signal for inverting the clock signal; a second inverter cascaded to the first inverter for outputting the clock signal; a signal protection unit including an input terminal coupled to the duty cycle signal for generating a break pulse to generate a protected duty cycle signal; a comparator including a positive input terminal coupled to a comparison signal of the power converter and a negative input terminal coupled to a triangle-wave signal for comparing the triangle-wave signal with the comparison signal to generate a comparison result; a NOR gate including a first input terminal coupled to the comparison result, and a second input terminal coupled to an output terminal of the signal protection unit for generating a reset signal according to the comparison result and the protected duty cycle signal; an SR-latch including a set input terminal coupled to an output terminal of the second inverter, a reset input terminal coupled to an output terminal of the NOR gate, and an output terminal for outputting a turn-on signal according to the clock signal and the reset signal; and an AND gate including a first input terminal coupled to the output terminal of the SR-latch, and a second input terminal coupled to the output terminal of the first inverter and the input terminal of the second inverter for generating the duty cycle signal according to the inverted clock signal and the turn-on signal; a drive stage circuit coupled to an output terminal of the duty cycle generator for outputting a switch signal according to the duty cycle signal; an output stage circuit coupled to an output terminal of the drive stage circuit for generating the output voltage according to the switch signal; and a feedback circuit coupled between the output stage circuit and the duty cycle generator for outputting the comparison signal to the duty cycle generator according to the output voltage. ### Claim 9 (depends on 8) The power converter of claim 8, further comprising a clock generator coupled to the duty cycle generator for generating the clock signal to the duty cycle generator. ### Claim 10 (depends on 8) The power converter of claim 8, wherein the drive stage circuit comprises: a first front-end driver including an input terminal coupled to the duty cycle signal, and an output terminal for generating a first front-end drive signal according to the duty cycle signal; a high-side switch including a drain coupled to the input voltage, a gate coupled to the output terminal of the first front-end driver, and a source for turning on or off the high-side switch according to the first front-end drive signal to generate the high-side switch turn-on signal; a second front-end driver including an input terminal coupled to the duty cycle signal, and an output terminal for generating a second front-end drive signal according to the duty cycle signal; and a low-side switch including a drain coupled to the input voltage, a gate coupled to the output terminal of the second front-end driver, and a source for turning on or off the low-side switch according to the second front-end drive signal. ### Claim 11 (depends on 8) The power converter of claim 8, wherein the output stage circuit comprises: an inductor coupled to an output terminal of the drive stage circuit for generating the output voltage; and an output capacitor coupled between the output terminal of the drive stage circuit and a ground. ### Claim 12 (depends on 8) The power converter of claim 8, wherein the feedback circuit comprises: an adjustment unit coupled to the inductor and the output capacitor for transferring the output voltage to a feedback voltage; and a comparator including a positive input terminal coupled to a reference signal, a negative input terminal coupled to the feedback voltage for comparing the feedback voltage with the reference signal to generate the comparison signal. ### Claim 13 (depends on 8) The power converter of claim 8, further comprising a compensation circuit coupled between the duty cycle generator and the feedback circuit, the compensation circuit comprising: a resistor coupled to the feedback voltage; a first capacitor coupled between the resistor and the comparison signal; and a second capacitor coupled between the feedback voltage and the comparison signal. ### Claim 14 (depends on 8) The power converter of claim 8, further comprising a triangle-wave generator for generating the triangle-wave signal. ### Claim 15 (depends on 8) The power converter of claim 8, wherein when the comparison signal is greater than the triangle-wave signal and the clock signal is at a high voltage, the duty cycle signal outputted by the AND gate is at a low voltage. ### Claim 16 (depends on 15) The power converter of claim 15, wherein when the comparison signal is greater than the triangle-wave signal and the clock signal is at a low voltage, the duty cycle signal outputted by the AND gate is at a high voltage. ### Claim 17 (depends on 16) The power converter of claim 16, wherein when the comparison signal is greater than the triangle-wave signal and the clock signal is at a low voltage, the break pulse is at a high voltage. ### Claim 18 (depends on 8) The power converter of claim 8, wherein a pulse width of the break pulse is less than a pulse width of the duty cycle signal. ### Claim 19 (depends on 8) The power converter of claim 8, wherein the power converter is a voltage mode power converter.