# US 8,570,015 B2 · DC-DC converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,570,015 B2 - Document ID: US8570015B2 - Status: Granted - Kind: B2 - Application number: 13/252,057 - Filed: 2011-10-03 - Published: 2012-01-26 - Granted: 2013-10-29 - Earliest claimed: 2008-01-04 - Assignees: Synopsys, Inc. - Applicants: Floriberto Amorim Azevedo Lima; Pedro Faria de Oliveira; Daniel Lourenco dos Santos - Inventors: Floriberto Amorim Azevedo Lima; Pedro Faria de Oliveira; Daniel Lourenco dos Santos - Web page: https://patentgrep.com/patent/US8570015B2 ## CPC - H02M 3/1588: {comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence)} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract A dual-mode switching voltage regulator has a duty cycle that varies with the input and output voltages so as to dynamically compensate for changes in the operating conditions. The switching voltage regulator uses input and output voltages/currents to optimize the duty cycle of the signals applied to a pair of switches disposed in the regulator. In the PFM mode, a control block senses the time that a first switch used to discharge an inductor is turned off. If the control block senses that the first switch is opened too early, the control block increases the on-time of a second switch used to charge the inductor. If the control block senses that the first switch is opened too late, the control block decreases the on-time of the second switch. ## Claims ### Claim 1 A switching voltage regulator comprising: an inductor; a first switch, responsive to a first signal, for charging the inductor during a first period; a second switch, responsive to a second signal, for discharging the inductor during a second period; a control block for varying a duty cycle of the first signal in accordance with a feedback signal representative of an output voltage of the switching voltage regulator; a first comparator for comparing a voltage across the second switch to a first voltage, determining a state of the second switch based on the comparing, and generating a first comparison signal; and a frequency-modulated pulse generator, wherein the control block further comprises a counter for incrementing its count when a transition between levels of the first comparison signal is detected as leading a corresponding transition of a target signal, and decrementing the count when the transition between levels of the first comparison signal is detected as lagging the corresponding transition of the target signal, and wherein the frequency-modulated pulse generator is adapted to vary the duty cycle of the first signal in accordance with the count. ### Claim 2 (depends on 1) The switching voltage regulator of claim 1, wherein the first comparator generates a the first comparison signal having a first level when the second switch is in a closed state and a current flowing through the second switch is above a predefined threshold value, generates the first comparison signal having the first level when the second switch is in an open state, and generates the first comparison signal having a second level when the second switch is in a closed state and the current flowing through the second switch is equal to or less than the predefined threshold value. ### Claim 3 (depends on 1) The switching voltage regulator of claim 1, wherein said first comparator further comprises: a current-to-voltage converter for converting a current flowing through the second switch to the voltage across the second switch, and comparing the converted voltage to the first voltage, wherein a result of the comparing determines whether the second switch is to maintain or change state. ### Claim 4 (depends on 1) The switching voltage regulator of claim 1, wherein the counter increments the count when a transition from a first level to a second level of the first comparison signal is detected as leading the corresponding transition of the target signal, and decrementing the count when the corresponding transition from the first level to the second level of the first comparison signal is detected as lagging the corresponding transition of the target signal, wherein the target signal is a clock signal. ### Claim 5 (depends on 1) The switching voltage regulator of claim 1, further comprising: a mode selector, responsive to said first comparator, for selecting between a pulse-width modulation and a pulse-frequency modulation mode of operation. ### Claim 6 (depends on 5) The switching voltage regulator of claim 5, wherein the mode selector switches from the pulse-width modulation mode to the pulse-frequency modulation mode of operation when a sum of the first and second periods is less than a predefined value for N consecutive switching periods of the switching voltage regulator, wherein N is an integer greater than 1. ### Claim 7 (depends on 6) The switching voltage regulator of claim 6, wherein the mode selector switches from the pulse-frequency modulation mode to the pulse-width modulation mode when following M consecutive switching periods, an output voltage of the switching voltage regulator does not reach a predefined level. ### Claim 8 (depends on 5) The switching voltage regulator of claim 5, wherein the control block varies the duty cycle of the first signal such that a sum of the first and second periods is substantially equal to a switching period of a switching voltage regulator. ### Claim 9 (depends on 4) The switching voltage regulator of claim 4, wherein the control block samples a state of the second switch for a configurable number of times before incrementing or decrementing the counter. ### Claim 10 (depends on 4) The switching voltage regulator of claim 4, further comprising circuitry for ensuring that the first and second switches are not in on states at a same time. ### Claim 11 A method of regulating an input voltage to generate an output voltage, the method comprising: applying a first signal to close a first switch during a first period to charge an inductor; applying a second signal to close a second switch during a second period to discharge the inductor; varying a duty cycle of the first signal in accordance with a feedback signal representative of the output voltage; comparing a voltage across the second switch to a first voltage to determine a state of the second switch; incrementing a count when a transition between levels of a first comparison signal is detected as leading a corresponding transition of a target signal; decrementing the count when the transition between levels of the first comparison signal is detected as lagging the corresponding transition of the target signal; and varying the duty cycle of the first signal in accordance with the count. ### Claim 12 (depends on 11) The method of claim 11, further comprising: generating the first comparison signal having a first level when the second switch is in a closed state and a current flowing through the second switch is greater than a predefined threshold value; generating the first comparison signal having the first level when the second switch is in an open state; and generating the first comparison signal having a second level when the second switch is in a closed state and the current flowing through the second switch is greater than equal to the predefined threshold value. ### Claim 13 (depends on 11) The method of claim 11, further comprising: incrementing the count when the transition from a second level to a first level of the first comparison signal is detected as leading the corresponding transition of the target signal; and decrementing the count when the transition from the second level to the first level of the first comparison signal is detected as lagging the corresponding transition of the target signal, wherein the target signal is a clock signal. ### Claim 14 (depends on 11) The method of claim 11, further comprising: converting a current flowing through the second switch to the voltage across the second switch. ### Claim 15 (depends on 11) The method of claim 11, further comprising: selecting between a pulse-width modulation mode and a pulse-frequency modulation mode of operation in response to a comparison signal. ### Claim 16 (depends on 15) The method of claim 15, further comprising: switching from the pulse-width modulation mode to the pulse-frequency modulation mode of operation when a sum of the first and second periods is less than a predefined value for N consecutive switching periods, wherein N is an integer greater than 1. ### Claim 17 (depends on 16) The method of claim 16, further comprising: switching from the pulse-frequency modulation mode to the pulse-width modulation mode of operation when following M consecutive switching periods, the output voltage does not reach a predefined level. ### Claim 18 (depends on 15) The method of claim 15, further comprising: disabling generation of the first and second signals when the feedback signal is detected as being less than a reference voltage. ### Claim 19 (depends on 11) The method of claim 11, further comprising: sampling a state of the second switch for a configurable number of times prior to incrementing or decrementing the count. ### Claim 20 (depends on 14) The method of claim 14, further comprising: placing the first switch in an open state prior to turning on the second switch. ### Claim 21 (depends on 11) The method of claim 11, further comprising: varying the duty cycle of the first signal such that a sum of the first period and the second period is substantially equal to a switching period.