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US 8,569,897 B2Granted
Protection layer for preventing UBM layer from chemical attack and oxidation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Shi Liu, Chien Ling Hwang, Ming-Che Ho
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Abstract
A protection layer formed of a CuGeyNz layer, a CuSixNz layer, a CuSixGeyNz layer or combinations thereof is formed on an under-bump metallurgy (UBM) layer for preventing the UBM layer from chemical attack and oxidation during subsequent processes.
Claims20
An integrated circuit device, comprising:
- a semiconductor substrate;
- a bond pad region overlying the semiconductor substrate;
- a metallization structure overlying and electrically connected to the bond pad region, wherein the metallization structure comprises a first metal layer overlying the bond pad region, a first protection layer on the first metal layer, and a second metal layer on the first metal layer;
- and
- a lead-free second protection layer contacting the sidewalls of the entire metallization structure,
- wherein the first protection layer is a first copper-containing layer comprising Ge, Si, N, or combinations thereof.
3 more elements
An integrated circuit device, comprising:
- a semiconductor substrate;
- a bond pad region overlying the semiconductor substrate;
- a passivation layer overlying the bond pad region and the semiconductor substrate, wherein the bond pad region comprises an uncovered portion not covered by the passivation layer;
- an under-bump metallurgy (UBM) layer formed on the uncovered portion of the bond pad region;
- a first protection layer on the UBM layer;
- a copper-containing post formed on the protection layer having sidewalls aligned with sidewalls of the UBM layer;
- a solder layer overlying the copper-containing post;
- and
- a second protection layer in direct contact with the sidewalls of the copper-containing post and overlying the solder layer,
- wherein the first protection layer is a copper-containing layer comprising Ge, Si, N, or combinations thereof.
7 more elements
An integrated circuit device, comprising:
- a semiconductor substrate;
- a bond pad region overlying the semiconductor substrate;
- a passivation layer overlying the bond pad region and the semiconductor substrate, wherein the bond pad region comprises an uncovered portion not covered by the passivation layer;
- an under-bump metallurgy (UBM) layer formed on the uncovered portion of the bond pad region;
- a protection layer on the UBM layer;
- a nickel-containing layer formed overlying the protection layer and exposing sidewalls of the protection layer;
- and
- a solder layer on the nickel-containing layer;
- wherein the protection layer is a copper-containing layer comprising at least one of Ge, Si, N, or combinations thereof.
6 more elements
Dependencies are inferred from the claim text.