Active area bonding compatible high current structures
AssigneeIntersil Americas Inc.
InventorsJohn T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
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Abstract
A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
Claims19
A semiconductor structure, the structure comprising:
- a top metal layer, the top metal layer including a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer,
- a bond pad formed on the top metal layer;
- a conductor formed below the top metal layer;
- and
- an insulation layer separating the conductor from the top metal layer;
- wherein the sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
A method of forming a semiconductor structure comprising:
- forming a top metal layer, wherein forming the top metal layer includes forming a sub-layer of the top of metal layer, the sub-layer being relatively stiff compared to the remaining portion of the top metal layer,
- forming a bond pad on a surface of the top metal layer;
- forming a conductor below the top metal layer;
- and
- forming an insulation layer separating the conductor from the top metal layer;
- wherein the sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
A semiconductor structure comprising:
- at least one electrical device in a substrate;
- one or more intermediate metal layers between a top metal layer and the substrate;
- one or more insulation layers, the one or more insulation layers separating the one or more intermediate metal layers and the top metal layer;
- and
- a passivation layer over the top metal layer;
- the passivation layer patterned to form a bond pad on a surface of the top metal layer, wherein the at least one electrical device is located directly under the bond pad;
- and
- wherein one of the one or more insulation layers is located adjacent to the top metal layer and has a thickness selected to resist cracking due to stresses caused by at least one of a bond wire attachment process or temperature excursions.
Dependencies are inferred from the claim text.