# US 8,569,894 B2 · Semiconductor package with single sided substrate design and manufacturing methods thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,569,894 B2
- Document ID: US8569894B2
- Status: Granted
- Kind: B2
- Application number: 13/006,340
- Filed: 2011-01-13
- Published: 2011-07-14
- Granted: 2013-10-29
- Earliest claimed: 2010-01-13
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Yuan-Chang Su; Shih-Fu Huang; Chia-Cheng Chen; Tzu-Hui Chen; Kuang-Hsiung Chen; Pao-Ming Hsieh; Ming Chiang Lee; Bernd Karl Appelt
- Inventors: Yuan-Chang Su; Shih-Fu Huang; Chia-Cheng Chen; Tzu-Hui Chen; Kuang-Hsiung Chen; Pao-Ming Hsieh; Ming Chiang Lee; Bernd Karl Appelt
- Web page: https://patentgrep.com/patent/US8569894B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/685: comprising multiple insulating layers
- H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 74/476: {Organic materials comprising silicon}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/656: Fan-in layouts
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07353: {changes in shapes}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/251: {Materials}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/354: {comprising polymers}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/931: {Shapes of bond pads}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49155: Manufacturing circuit on or in base
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

## Claims

### Claim 1

A semiconductor package, comprising:
a substrate unit including:
a first patterned conductive layer having an upper surface;
a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a part of the first patterned conductive layer to form a plurality of first contact pads;
a second patterned conductive layer below the first patterned conductive layer and having a lower surface;
a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein:
the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and
the second patterned conductive layer includes a plurality of second contact pads exposed by the second dielectric layer; and
a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to a corresponding one of the plurality of second contact pads through a corresponding one of the plurality of openings in the second dielectric layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer;
wherein at least one of the plurality of conductive posts defines a cavity, and wherein the cavity is filled by a part of the first dielectric layer;
a die electrically connected to the plurality of first contact pads; and
a package body covering the first patterned conductive layer and the die.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein:
each of the plurality of conductive posts has an upper surface having a first area and a lower surface having a second area; and
each of the plurality of second contact pads has an upper surface having a third area;
wherein the first area is larger than the second area, and wherein the third area is larger than the second area.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein:
the second dielectric layer has a lower surface; and
the lower surface of the second patterned conductive layer is recessed from the lower surface of the second dielectric layer.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein:
the first patterned conductive layer includes a ground plane positioned between the first dielectric layer and the second dielectric layer;
at least one of the plurality of openings defined by the second dielectric layer extends from the ground plane to the second patterned conductive layer; and
at least one of the plurality of conductive posts extends from the ground plane to at least one of the plurality of second contact pads through the at least one of the plurality of openings in the second dielectric layer.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein the ground plane includes a mesh portion.

### Claim 6 (depends on 4)

The semiconductor package of claim 4, wherein:
the die is connected to the at least one of the plurality of second contact pads through the ground plane and the at least one of the plurality of conductive posts to provide the die electrical connectivity to ground and to facilitate heat dissipation from the semiconductor package.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein a conductive element is disposed in the recess.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the die is flip chip bonded to the plurality of first contact pads.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the die is connected to the plurality of first contact pads by a plurality of fused conductive bumps extending through the first dielectric layer.

### Claim 10

A semiconductor package, comprising:
a substrate unit including:
a first patterned conductive layer having an upper surface;
a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a part of the first patterned conductive layer to form a plurality of first contact pads;
a second patterned conductive layer below the first patterned conductive layer and having a lower surface;
a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein:
the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and
the second patterned conductive layer includes a plurality of second contact pads exposed by the second dielectric layer; and
a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to a corresponding one of the plurality of second contact pads through a corresponding one of the plurality of openings in the second dielectric layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer;
wherein at least one of the plurality of conductive posts defines a cavity;
a die electrically connected to the plurality of first contact pads, wherein the die is flip chip bonded to the plurality of first contact pads, wherein the die is connected to the plurality of first contact pads by a plurality of fused conductive bumps, and wherein the cavity is filled by a part of at least one of the plurality of fused conductive bumps; and
a package body covering the first patterned conductive layer and the die.

### Claim 11

A method of manufacturing a substrate, comprising:
providing a carrier having an upper surface and a lower surface, and with a first conductive sheet formed adjacent to the upper surface of the carrier;
forming a first plurality of conductive blocks made of copper or copper alloy extending vertically from the first conductive sheet, each of the first plurality of conductive blocks having an upper surface;
forming a first dielectric layer that defines a first plurality of openings, each of the first plurality of openings exposing a part of the upper surface of a corresponding one of the first plurality of conductive blocks; and
forming a first plurality of conductive posts and a first patterned conductive layer, each of the first plurality of conductive posts extending from a corresponding one of the first plurality of conductive blocks to the first patterned conductive layer and filling a corresponding one of the first plurality of openings.

### Claim 12 (depends on 11)

The method of claim 11 further comprising removing the carrier to expose the first conductive sheet and then removing a portion of the first conductive sheet.

### Claim 13 (depends on 11)

The method of claim 11, further comprising removing the carrier to expose the first conductive sheet and then attaching a support member to the first conductive sheet .

### Claim 14 (depends on 11)

The method of claim 11, wherein the first conductive sheet includes a metal foil and a barrier sublayer formed adjacent to the metal foil, such that the first plurality of conductive blocks extend vertically from the barrier sublayer.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first conductive sheet has a thickness in the range from 2 μm to 20 μm.

### Claim 16 (depends on 11)

The method of claim 11, wherein a second conductive sheet is formed adjacent to the lower surface of the carrier, and further comprising:
forming a second plurality of conductive blocks made of copper or copper alloy extending vertically from the second conductive sheet, each of the second plurality of conductive blocks having a lower surface;
forming a second dielectric layer that defines a second plurality of openings, each of the second plurality of openings exposing a part of the lower surface of a corresponding one of the second plurality of conductive blocks; and
forming a second plurality of conductive posts and a second patterned conductive layer, each of the second plurality of conductive posts extending from a corresponding one of the second plurality of conductive blocks to the second patterned conductive layer and filling a corresponding one of the second plurality of openings.

### Claim 17 (depends on 11)

The method of claim 11, further comprising removing a portion of the first plurality of conductive blocks to form a plurality of contact pads for electrical connection externally.

### Claim 18 (depends on 11)

The method of claim 11, wherein forming the first dielectric layer includes:
disposing a dielectric layer covering the first conductive sheet and the first plurality of conductive blocks, wherein the dielectric layer is positioned between a second conductive sheet and the first plurality of conductive blocks;
patterning the second conductive sheet to expose portions of the dielectric layer; and
removing the exposed portions of the dielectric layer to form the first plurality of openings.

### Claim 19 (depends on 18)

The method of claim 18, wherein disposing the dielectric layer includes covering the first conductive sheet and the first plurality of conductive blocks with at least one of a patterned prepreg layer and a resin coated copper film.

### Claim 20 (depends on 18)

The method of claim 18, wherein disposing the dielectric layer includes printing a layer of at least one of solder mask and epoxy to cover the first conductive sheet and the first plurality of conductive blocks.

### Claim 21

A method of manufacturing a semiconductor package, comprising:
providing a substrate including:
a conductive sheet;
a plurality of conductive blocks made of copper or copper alloy extending vertically from the conductive sheet, each of the plurality of conductive blocks having an upper surface;
a dielectric layer that defines a plurality of openings, each of the plurality of openings exposing a part of the upper surface of a corresponding one of the plurality of conductive blocks;
a patterned conductive layer; and
a plurality of conductive posts, each of the plurality of conductive posts extending from a corresponding one of the plurality of conductive blocks to the patterned conductive layer and filling a corresponding one of the plurality of openings;
electrically connecting a die to the patterned conductive layer;
forming a package body covering the dielectric layer and the die; and
removing the conductive sheet to expose the plurality of conductive blocks.

### Claim 22 (depends on 21)

The method of claim 21, wherein the conductive sheet includes:
a metal foil; and
a barrier sublayer adjacent to the metal foil and positioned between the metal foil and the plurality of conductive blocks.

### Claim 23 (depends on 22)

The method of claim 22, wherein removing the conductive sheet includes:
removing the metal foil to expose the barrier sublayer; and
removing the barrier sublayer to expose the plurality of conductive blocks.

### Claim 24 (depends on 22)

The method of claim 22, wherein the metal foil has a thickness in the range from 2 μm to 20 μm.

### Claim 25 (depends on 21)

The method of claim 21, wherein providing the substrate comprises:
providing a carrier having an upper surface and a lower surface, and with the conductive sheet formed adjacent to the upper surface of the carrier;
forming the plurality of conductive blocks extending vertically from an upper surface of the conductive sheet;
forming the dielectric layer, the dielectric layer defining the plurality of openings, each of the plurality of openings exposing a part of the upper surface of a corresponding one of the plurality of conductive blocks; and
forming the plurality of conductive posts and the patterned conductive layer, each of the plurality of conductive posts extending from the upper surface of the corresponding one of the plurality of conductive blocks to the patterned conductive layer and filling a corresponding one of the plurality of openings.

### Claim 26 (depends on 25)

The method of claim 25, wherein forming the patterned conductive layer comprises:
forming a first conductive sublayer adjacent to the plurality of conductive blocks;
forming a patterned dry film adjacent to the first conductive sublayer;
forming a second conductive sublayer adjacent to the first conductive sublayer;
forming a cavity extending through at least the second conductive sublayer, the cavity associated with a corresponding one of the plurality of conductive blocks; and
disposing the dielectric layer adjacent to the patterned conductive layer, a part of the first dielectric layer filling the cavity.

### Claim 27

A substrate, comprising:
a first patterned conductive layer having an upper surface;
a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a part of the first patterned conductive layer to form a plurality of first contact pads;
a second patterned conductive layer below the first patterned conductive layer and having a lower surface;
a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein:
the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and
the second patterned conductive layer includes a plurality of second contact pads and at least one trace;
a third dielectric layer disposed on the second dielectric layer, the third dielectric layer exposing at least one of the plurality of the second contact pads and covering the at least one trace; and
a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to a corresponding one of the plurality of second contact pads through a corresponding one of the plurality of openings in the second dielectric layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer.

### Claim 28 (depends on 27)

The substrate of claim 27, wherein there is a lateral displacement of one of the plurality of second conductive pads relative to at least one of the conductive posts.

### Claim 29 (depends on 27)

The substrate of claim 27, wherein:
the second dielectric layer has a lower surface; and
the lower surface of the second patterned conductive layer is recessed from the lower surface of the second dielectric layer.