# US 8,569,887 B2 · Post passivation interconnect with oxidation prevention layer

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- Number: US 8,569,887 B2
- Document ID: US8569887B2
- Status: Granted
- Kind: B2
- Application number: 12/907,249
- Filed: 2010-10-19
- Published: 2011-05-05
- Granted: 2013-10-29
- Earliest claimed: 2009-11-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Chien Ling Hwang; Yi-Wen Wu; Chung-Shi Liu
- Inventors: Chien Ling Hwang; Yi-Wen Wu; Chung-Shi Liu
- Web page: https://patentgrep.com/patent/US8569887B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/48: Insulating materials thereof
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 72/01215: {forming coatings}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01255: {by using masks}
- H10W 72/01257: {by reflowing}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/0198: {batch processes}
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings}
- H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A copper interconnect line formed on a passivation layer is protected by a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof.

## Claims

### Claim 1

An integrated circuit device, comprising:
a semiconductor substrate;
a passivation layer overlying the semiconductor substrate;
a polymer layer overlying the passivation layer;
an interconnect line formed between the passivation layer and the polymer layer, the interconnect line extending over a top surface of the passivation layer; and
a protection layer formed between the interconnect line and the polymer layer;
wherein the protection layer is a copper-containing material layer comprising at least one of a group III element, a group IV element and a group V element.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein the protection layer is a CuGeN layer.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1, wherein the copper-containing material layer comprises at least one of germanium (Ge), silicon (Si) or carbon (C).

### Claim 4 (depends on 1)

The integrated circuit device of claim 1, wherein the copper-containing material layer comprises at least one of nitrogen (N) or phosphorus (P).

### Claim 5 (depends on 1)

The integrated circuit device of claim 1, wherein the copper-containing material layer comprises boron (B).

### Claim 6 (depends on 1)

The integrated circuit device of claim 1, wherein the interconnect line comprises copper.

### Claim 7 (depends on 1)

The integrated circuit device of claim 1, wherein the polymer layer comprises polyimide or polybenzoxazole (PBO).

### Claim 8 (depends on 1)

The integrated circuit device of claim 1, wherein the passivation layer has an opening exposing a portion of the semiconductor substrate, and the interconnect line is formed on a portion of the passivation layer and fills the opening of the passivation layer.

### Claim 9 (depends on 8)

The integrated circuit device of claim 8, further comprising a Ti layer underlying the interconnect line and lining the bottom and sidewalls of the opening of the passivation layer.

### Claim 10 (depends on 9)

The integrated circuit device of claim 9, further comprising a copper layer formed between the interconnect line and the Ti layer.

### Claim 11 (depends on 1)

The integrated circuit device of claim 1, wherein the polymer layer has an opening exposing a portion of the protection layer.

### Claim 12 (depends on 11)

The integrated circuit device of claim 11, further comprising a bump structure overlying the polymer layer and electrically connected to the protection layer through the opening of the polymer layer.

### Claim 13 (depends on 12)

The integrated circuit device of claim 12, wherein the bump structure comprises a copper post.

### Claim 14 (depends on 13)

The integrated circuit device of claim 13, wherein the bump structure comprises a cap layer on the copper post.

### Claim 15 (depends on 14)

The integrated circuit device of claim 14, wherein the cap layer comprises at least one of a nickel-containing layer, a tin-containing layer or combinations thereof.

### Claim 16 (depends on 12)

The integrated circuit device of claim 12, wherein the bump structure comprises a tin-containing layer on sidewalls of a copper post.

### Claim 17

An integrated circuit device, comprising:
a semiconductor substrate comprising a contact region;
a passivation layer overlying the semiconductor substrate and having an opening exposing a portion of the contact region;
a copper line overlying a portion of the passivation layer and filling the opening, electrically connected to the contact region; and
a protection layer formed on a surface of the copper line and contacting sidewalls of the copper line, wherein the protection layer is a copper-containing material layer comprising at least one of a group III element, a group IV element, or a group V element.

### Claim 18 (depends on 17)

The integrated circuit device of claim 17, wherein the protection layer is at least one of a CuGeN layer, a CuGe layer, a CuSi layer, a CuSiN layer, a CuSiGeN layer, a CuN layer, a CuP layer, a CuC layer, a CuB layer, and any combination thereof.

### Claim 19 (depends on 17)

The integrated circuit device of claim 17, further comprising a Cu post on the protection layer.

### Claim 20

An integrated circuit device, comprising:
a semiconductor substrate;
a passivation layer overlying the semiconductor substrate;
a polymer layer overlying the passivation layer, a portion of the polymer layer in direct contact with a portion of the passivation layer;
an interconnect line formed between the passivation layer and the polymer layer; and
a protection layer formed between the interconnect line and the polymer layer;
wherein the protection layer is a copper-containing material layer comprising at least one of a group III element, a group IV element and a group V element.