# US 8,569,883 B2 · Package for high power devices

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- Number: US 8,569,883 B2
- Document ID: US8569883B2
- Status: Granted
- Kind: B2
- Application number: 13/229,487
- Filed: 2011-09-09
- Published: 2012-01-05
- Granted: 2013-10-29
- Earliest claimed: 2006-12-19
- Assignees: International Rectifier Corporation
- Applicants: Henning M. Hauenstein
- Inventors: Henning M. Hauenstein
- Web page: https://patentgrep.com/patent/US8569883B2

## CPC

- H10W 42/80: protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10D 1/47: Resistors having no potential barriers
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 40/10: Arrangements for heating
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/692: Ceramics or glasses
- H10W 90/00: Package configurations
- H10W 72/0198: {batch processes}
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07327: {involving guiding structures, e.g. spacers or supporting members}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07355: {changes in materials}
- H10W 72/075: {of bond wires}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/3528: {Intermetallic compounds}
- H10W 72/387: {Flow barriers}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/732: {between stacked chips}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

## Claims

### Claim 1

A semiconductor device package comprising:
a semiconductor die having first and second parallel surfaces and a support can;
said support can comprising an insulation body having top and bottom parallel surfaces with corresponding top and bottom conductive layers;
said top conductive layer having a depression therein defining a web surface and a rim portion extending around at least a portion of the periphery of said web surface;
said web surface having a plurality of dimples formed therein defining a perimeter of a desired location for said semiconductor die;
said semiconductor die being disposed in said desired location in said depression.

### Claim 2 (depends on 1)

The semiconductor device package of claim 1, wherein said semiconductor die is a silicon MOSgated device.

### Claim 3 (depends on 1)

The semiconductor device package of claim 1, wherein said semiconductor die is an IGBT.

### Claim 4 (depends on 1)

The semiconductor device package of claim 1 further comprising an electrode on at least one of said first and said second parallel surfaces of said semiconductor die, said electrode being mechanically and electrically fixed to said web surface.

### Claim 5 (depends on 4)

The semiconductor device package of claim 4, wherein said electrode is a drain electrode.

### Claim 6 (depends on 4)

The semiconductor device package of claim 4, wherein said electrode is a source electrode.

### Claim 7 (depends on 4)

The semiconductor device package of claim 4, wherein said electrode is a bump contact.

### Claim 8 (depends on 4)

The semiconductor device package of claim 4, wherein said electrode is a solderable pad.

### Claim 9 (depends on 1)

The semiconductor device package of claim 1, wherein said rim portion has a general U shape.

### Claim 10 (depends on 1)

The semiconductor device package of claim 1, wherein said support can is a DBC wafer.

### Claim 11 (depends on 1)

The semiconductor device package of claim 1, wherein said insulation body is ceramic.

### Claim 12 (depends on 1)

The semiconductor device package of claim 1, wherein said top and bottom conductive layers comprise copper.

### Claim 13 (depends on 4)

The semiconductor device package of claim 4, wherein said electrode is soldered to a surface of said depression.

### Claim 14 (depends on 1)

The semiconductor device package of claim 1, wherein said rim portion is open at its opposite ends.

### Claim 15 (depends on 1)

The semiconductor device package of claim 1 further comprising a heat sink being electrically and mechanically fixed to said bottom conductive layer.

### Claim 16 (depends on 15)

The semiconductor device package of claim 15 further comprising fluid coolant channels in said heat sink.

### Claim 17 (depends on 1)

The semiconductor device package of claim 1 further comprising at least one via in said insulation body.

### Claim 18 (depends on 4)

The semiconductor device package of claim 4 further comprising an integrated circuit device having at least one terminal connected to said electrode.