# US 8,569,879 B2 · Accessing or interconnecting integrated circuits

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- Number: US 8,569,879 B2
- Document ID: US8569879B2
- Status: Granted
- Kind: B2
- Application number: 13/351,142
- Filed: 2012-01-16
- Published: 2012-05-10
- Granted: 2013-10-29
- Earliest claimed: 2007-05-04
- Assignees: CrossFire Technologies, Inc.
- Applicants: Kevin Atkinson; Clifford H. Boler
- Inventors: Kevin Atkinson; Clifford H. Boler
- Web page: https://patentgrep.com/patent/US8569879B2

## CPC

- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- H03K 19/017581: {programmable}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/641: {Adaptable interconnections, e.g. fuses or antifuses}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/07254: {changes in dispositions}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and (programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.

## Claims

### Claim 1

An apparatus comprising:
laterally attached diced first and second integrated circuit die, respectively having a length, a width, and a height, wherein the length and width define a face area greater than an lateral edge area defined by the height and one of the length and width, wherein the lateral edges of the first and second die are laterally attached to each other; and
a monolithic first insulator layer extending over the first and second integrated circuit die and over the lateral attachment between the first and second integrated circuit die, a first via extending through the monolithic first insulator layer and over and electrically connecting to a plurality of conductive input/output structures on the first integrated circuit that are configured to respectively carry distinct signals, and wherein the first integrated circuit includes a programming circuit to select which of the plurality of conductive input/output structures under the first via on the first integrated circuit electrically conductively communicates with the second integrated circuit using the first via.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the plurality of conductive input/output structures comprises a first conductive input/output structure comprising a lateral dimension that is sized to substantially match a minimum linewidth design rule of a semiconductor process forming a conductive layer of the first conductive input/output structure.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the plurality of conductive input/output structures comprises a second conductive input/output structure that is separated from the first conductive input/output structure by a lateral dimension that is sized to substantially match a minimum separation design rule of a semiconductor process forming the conductive layer of the first and second conductive input/output structures.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein:
the plurality of conductive input/output structures on the first integrated circuit comprises a two-dimensional I/O array of the conductive first input/output structures, the two dimensional I/O array defining a first area; and
the first via is included in a two-dimensional via array of vias in the first insulator, the two-dimensional via array defining a second area, wherein the first area is larger than the second area.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the first area is larger than the second area by an amount that accommodates an error tolerance of a integrated circuit die pick-and-place apparatus, such that the second area is overlaid within the first area when the first integrated circuit is placed into position using the pick-and-place apparatus.

### Claim 6 (depends on 4)

The apparatus of claim 4, comprising:
a first two-dimensional alignment array of addressable contacts;
a first alignment via in the first insulator, the first alignment via sized for connecting to a single one of the addressable contacts in the first two-dimensional alignment array; and
and an alignment detection circuit, configured address the contacts in the first two-dimensional alignment array to determine alignment information based upon determining which of the contacts in the first two-dimensional alignment array is aligned to and electrically connected with the first alignment via.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the programming circuit is coupled to the alignment detection circuit and configured to use alignment information from the alignment detection circuit to select which of the plurality of conductive input/output structures under the first via on the first integrated circuit electrically conductively communicates with the second integrated circuit using the first via.

### Claim 8 (depends on 6)

The apparatus of claim 6, comprising:
a second two-dimensional alignment array of addressable contacts;
a second alignment via in the first insulator, the second alignment via sized for connecting to a single one of the addressable contacts in the second two-dimensional alignment array; and
wherein the alignment detection circuit is also configured address the contacts in the second two-dimensional alignment array to determine the alignment information based upon determining which of the contacts in the second two-dimensional alignment array is aligned to and electrically connected with the second alignment via.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the first and second two-dimensional alignment arrays are located on the first integrated circuit with a plurality of the conductive input/output structures on the first integrated circuit located between the first and second two-dimensional alignment arrays.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the first integrated circuit die includes a first conductive line extending in a first direction, and comprising a via in the monolithic first insulator extending in a second direction, orthogonal to the first direction, the via including a via dimension in the second direction that exceeds a mechanical IC die pick-and-place error tolerance in the second direction.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the first insulator includes the first via.

### Claim 12 (depends on 1)

The apparatus of claim 1, comprising a third integrated circuit die at least partially overlying the first integrated circuit die includes the first via.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the first via includes a through-substrate via (TSV).

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the plurality of conductive input/output structures on the first integrated circuit includes a plurality of bumped or raised I/O structures that are electrically coupled to the first via.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein the TSV includes a second metal layer extending from a working surface of the third integrated circuit die, facing the first integrated circuit die, to a backside of the third integrated circuit die, facing away from the first integrated circuit die.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the third integrated circuit die includes a plurality of conductive bumped or raised input/output structures on a backside of the third integrated circuit die facing away from the first integrated circuit die.

### Claim 17 (depends on 16)

The apparatus of claim 16, comprising a fourth integrated circuit die at least partially overlying the third integrated circuit die, wherein the fourth integrated circuit die includes a second via that is electrically coupled to the plurality of conductive bumped or raised input/output structures on the backside of the third integrated circuit die.

### Claim 18 (depends on 13)

The apparatus of claim 13, wherein the first via includes a bumped or raised electrical connection.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the plurality of conductive input/output structures on the first integrated circuit includes a plurality of bumped or raised I/O structures that are electrically coupled to the bumped or raised electrical connection of the first via.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the plurality of conductive input/output structures on the first integrated circuit includes a plurality of bumped or raised I/O structures that are removably thermally bonded to the bumped or raised electrical connection of the first via.