# US 8,569,878 B2 · Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,878 B2 - Document ID: US8569878B2 - Status: Granted - Kind: B2 - Application number: 12/588,659 - Filed: 2009-10-22 - Published: 2011-04-28 - Granted: 2013-10-29 - Earliest claimed: 2009-10-22 - Assignees: Headway Technologies, Inc.; SAE Magnetics (H.K.) Ltd. - Applicants: Yoshitaka Sasaki; Hiroyuki Ito; Atsushi Iijima - Inventors: Yoshitaka Sasaki; Hiroyuki Ito; Atsushi Iijima - Web page: https://patentgrep.com/patent/US8569878B2 ## CPC - H10W 90/00: Package configurations - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/0198: {batch processes} - H10W 74/01: Manufacture or treatment - H10W 74/129: {forming a chip-scale package [CSP]} - H10P 72/7438: {with parts of the auxiliary support remaining in the finished device} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/30: Die-attach connectors - H10W 72/834: {Interconnections on sidewalls of chips} - H10W 72/874: {On different surfaces} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; and a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above a surface of the surface insulating layer. The semiconductor substrate can be manufactured by forming a plurality of groove portions along scribe lines; applying an insulating material to a surface on a side where the plurality of groove portions are formed to form a surface insulating layer; and forming a wiring electrode connected to the semiconductor device and in a protruding shape rising above a surface of the surface insulating layer, after the formation of the surface insulating layer. ## Claims ### Claim 1 A semiconductor substrate having a plurality of groove portions formed along scribe lines, comprising: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above an outer surface of the surface insulating layer; and an in-groove insulating portion formed inside the groove portions, wherein the outer surface of the surface insulating layer and a surface of the in-groove insulating portion are substantially parallel throughout an upper surface of the device region arranged near the wiring electrode, the surface insulating layer is disposed at the outermost position of the semiconductor substrate, except at portions where the wiring electrodes are formed, and a plurality of the wiring electrodes are arranged along at least any one of the plurality of groove portions and form a wiring electrode group having an unevenly distributed structure in which extended terminal portions thereof are unevenly extended at a part of all of the groove portions in contact with the device region. ### Claim 2 (depends on 1) The semiconductor substrate according to claim 1, wherein the wiring electrode has a cross side surface projecting outward from the surface of the surface insulating layer and crossing with the surface of the surface insulating layer, a top end face projecting outward from the surface of the surface insulating layer and disposed along the surface of the surface insulating layer, and an embedded portion embedded inward from the surface of the surface insulating layer. ### Claim 3 (depends on 1) The semiconductor substrate according to claim 1, further comprising: a connecting pad connected to the semiconductor device; and a protecting insulating layer having a connecting hole formed at a position for forming the connecting pad, the protecting insulating layer being disposed under the surface insulating layer and formed to cover the device region, wherein the wiring electrode has an electrode pad having an expanded height from a side outer than the surface of the surface insulating layer to the connecting pad. ### Claim 4 (depends on 1) The semiconductor substrate according to claim 1, wherein an end face of the wiring electrode appears projecting outward from the surface of the surface insulating layer at a cut surface when the semiconductor substrate is cut along at least any one of the plurality of groove portions. ### Claim 5 (depends on 1) The semiconductor substrate according to claim 1, wherein the wiring electrode has an extended terminal portion that is substantially parallel throughout the upper surface of the device region. ### Claim 6 A semiconductor substrate having a plurality of groove portions formed along scribe lines, comprising: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; and a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above an outer surface of the surface insulating layer, wherein the surface insulating layer is structured integrally with an in-groove insulating portion formed inside the groove portion, the wiring electrode has an extended terminal portion extended from the device region to an area above the groove portion and formed in a protruding shape rising above an outer surface of the in-groove insulating portion, the groove portions are entirely filled with the in-groove insulating portion portion, and a plurality of the wiring electrodes are arranged along at least any one of the plurality of groove portions and form a wiring electrode group having an unevenly distributed structure in which the respective extended terminal portions thereof are unevenly extended at a part of all of the groove portions in contact with the device region. ### Claim 7 (depends on 6) The semiconductor substrate according to claim 6, wherein the extended terminal portion has a cross side surface projecting outward from the surface of the surface insulating layer and crossing with the surface of the surface insulating layer, and a top end face projecting outward from the surface of the surface insulating layer and disposed along the surface of the surface insulating layer. ### Claim 8 (depends on 7) The semiconductor substrate according to claim 7, further comprising: a connecting pad connected to the semiconductor device; and a protecting insulating layer having a connecting hole formed at a position for forming the connecting pad, the protecting insulating layer being disposed under the surface insulating layer and formed to cover the device region, wherein the wiring electrode has an electrode pad having an expanded height higher than the surface of the surface insulating layer above the connecting pad. ### Claim 9 (depends on 6) The semiconductor substrate according to claim 6, wherein the extended terminal portion is not in contact with another conductive part in an area above the groove portions. ### Claim 10 A semiconductor substrate having a plurality of groove portions formed along scribe lines, comprising: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; and a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above an outer surface of the surface insulating layer; wherein the surface insulating layer is structured integrally with an in-groove insulating portion formed inside the groove portion, the wiring electrode has an extended terminal portion extended from the device region to an area above the groove portion and formed in a protruding shape rising above an outer surface of the in-groove insulating portion, and a plurality of the wiring electrodes are arranged along at least any one of the plurality of groove portions and form a wiring electrode group having an unevenly distributed structure in which the respective extended terminal portions thereof are unevenly extended at a part of all of the groove portions in contact with the device region.