# US 8,569,876 B2 · Packaged semiconductor chips with array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,876 B2 - Document ID: US8569876B2 - Status: Granted - Kind: B2 - Application number: 11/603,935 - Filed: 2006-11-22 - Published: 2008-05-22 - Granted: 2013-10-29 - Earliest claimed: 2006-11-22 - Assignees: Tessera, Inc. - Applicants: Andrey Grinman; David Ovrutsky; Charles Rosenstein; Vage Oganesian - Inventors: Andrey Grinman; David Ovrutsky; Charles Rosenstein; Vage Oganesian - Web page: https://patentgrep.com/patent/US8569876B2 ## CPC - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes} - H10W 42/25: against alpha rays, e.g. for outer space applications - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 74/40: characterised by their materials - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/635: {Through-vias} - H10W 70/688: {Flexible insulating substrates} - H10W 72/01331: {using blanket deposition} - H10W 72/801: {Interconnections on sidewalls of containers} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device. ## Claims ### Claim 1 A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface; at least one packaging layer containing silicon and formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface; a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads; and a second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer, wherein the die has a thickness extending from the first surface to the second surface, and wherein the first ball grid array is aligned with the second ball grid array in a direction of the thickness of the die. ### Claim 2 (depends on 1) A chip-sized, wafer level packaged device according to claim 1 and wherein said at least one packaging layer comprises a plurality of packaging layers. ### Claim 3 (depends on 2) A chip-sized, wafer level packaged device according to claim 2 and wherein said plurality of packaging layers are disposed on the same side of said die. ### Claim 4 (depends on 1) A chip-sized wafer level packaged device according to claim 1 and wherein said device is a DRAM device. ### Claim 5 (depends on 1) A chip-sized wafer level packaged device according to claim 1 and also comprising a first compliant layer, formed over said packaging layer and underlying said first ball grid array. ### Claim 6 (depends on 5) A chip-sized wafer level packaged device according to claim 5, wherein said first conductors are formed over said first compliant layer and are underlying said first ball grid array. ### Claim 7 (depends on 5) A chip-sized wafer level packaged device according to claim 5 and wherein said first compliant layer includes at least one of silicone or a polymeric dielectric material. ### Claim 8 (depends on 7) A chip-sized wafer level packaged device according to claim 7 and wherein said polymeric material comprises a polyimide. ### Claim 9 (depends on 5) A chip-sized wafer level packaged device according to claim 5 and also comprising a second compliant layer, formed over said first surface of said die and underlying said second ball grid array. ### Claim 10 (depends on 9) A chip-sized wafer level packaged device according to claim 9, wherein said second conductors are formed over said second compliant layer and are underlying said second ball grid array. ### Claim 11 (depends on 9) A chip-sized wafer level packaged device according to claim 9 and wherein said first compliant layer includes at least one of silicone or a polymeric dielectric material. ### Claim 12 (depends on 11) A chip-sized wafer level packaged device according to claim 11 and wherein said polymeric material comprises a polyimide. ### Claim 13 (depends on 1) A chip-sized wafer level packaged device according to claim 1 and wherein alpha-particle shielding is provided between at least one of said first or second ball grid arrays and said device. ### Claim 14 (depends on 1) A chip-sized wafer level packaged device according to claim 1, wherein said at least one packaging layer includes a first packaging layer, said packaged device further comprising: a second packaging layer formed over said second surface of said die, wherein said first ball grid array is formed on said first packaging layer and said second ball grid array is formed on said second packaging layer. ### Claim 15 (depends on 14) A chip-sized wafer level packaged device according to claim 14, further comprising: first compliant layer formed on said first packaging layer and underlying said first ball grid array; second compliant layer formed on said second packaging layer and underlying said second ball grid array. ### Claim 16 (depends on 15) A chip-sized wafer level packaged device according to claim 15, wherein at least one of said compliant layers provides alpha-particle shielding between at least one of said first or second ball grid arrays and said device. ### Claim 17 (depends on 15) A chip-sized wafer level packaged device according to claim 15, wherein at least one of said compliant layers comprises a layer of an electrophoretic material. ### Claim 18 (depends on 1) A chip-sized, wafer level packaged device according to claim 1, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. ### Claim 19 A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface; at least one packaging layer formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface; a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads; a second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer; and a compliant electrophoretic coating layer underlying at least one of said first or second ball grid arrays, wherein the die has a thickness extending from the first surface to the second surface, and wherein the first ball grid array is aligned with the second ball grid array in a direction of the thickness of the die. ### Claim 20 (depends on 19) A chip-sized wafer level packaged device according to claim 19 and wherein said at least one packaging layer contains silicon. ### Claim 21 (depends on 19) A chip-sized wafer level packaged device according to claim 19 and wherein said compliant electrophoretic coating layer provides alpha-particle shielding between the at least one of said first or second ball grid arrays and said device. ### Claim 22 (depends on 19) A chip-sized wafer level packaged device according to claim 19 and wherein said device is a DRAM device. ### Claim 23 (depends on 19) A chip-sized, wafer level packaged device according to claim 19 and wherein said at least one packaging layer comprises a plurality of packaging layers. ### Claim 24 (depends on 23) A chip-sized, wafer level packaged device according to claim 23 and wherein said plurality of packaging layers are disposed on the same side of said die. ### Claim 25 (depends on 19) A chip-sized wafer level packaged device according to claim 19, and also comprising metal connections formed over said compliant electrophoretic coating layer and underlying the at least one of said first or second ball grid arrays, said metal connections providing electrical contact between the at least one of said first or second ball grid arrays and said device. ### Claim 26 (depends on 19) A chip-sized wafer level packaged device according to claim 19 and wherein said compliant electrophoretic coating layer includes at least one of silicone or a polymeric dielectric material. ### Claim 27 (depends on 26) A chip-sized wafer level packaged device according to claim 26 and wherein said polymeric material comprises a polyimide. ### Claim 28 (depends on 19) A chip-sized wafer level packaged device according to claim 19, wherein said at least one packaging layer includes a first packaging layer, said packaged device further comprising: a second packaging layer formed over said second surface of said die, wherein said first ball grid array is formed on said first packaging layer and said second ball grid array is formed on said second packaging layer. ### Claim 29 (depends on 28) A chip-sized wafer level packaged device according to claim 28, wherein said compliant electrophoretic coating layer comprises: first compliant electrophoretic coating layer formed on said first packaging layer and underlying said first ball grid array; second compliant electrophoretic coating layer formed on said second packaging layer and underlying said second ball grid array. ### Claim 30 (depends on 29) A chip-sized wafer level packaged device according to claim 29, wherein said first and second electrophoretic coating layers provide alpha-particle shielding between said first and second ball grid arrays and said device. ### Claim 31 (depends on 19) A chip-sized, wafer level packaged device according to claim 19, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. ### Claim 32 Stacked chip-sized, wafer level packaged devices comprising: at least first and second chip-sized wafer level packaged devices each including: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface, at least one packaging layer containing silicon and formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface, a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads, and a second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer, and wherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer; and said first ball grid array of said first device being coupled to said second ball grid array of said second device. ### Claim 33 (depends on 32) Stacked chip-sized, wafer level packaged devices according to claim 32 and wherein said at least one packaging layer comprises a plurality of packaging layers. ### Claim 34 (depends on 33) Stacked chip-sized, wafer level packaged devices according to claim 33 and wherein said plurality of packaging layers are disposed on the same side of said portion of said semiconductor wafer. ### Claim 35 (depends on 32) A chip-sized wafer level packaged device according to claim 32 and wherein said device is a DRAM device. ### Claim 36 Stacked chip-sized, wafer level packaged devices comprising: at least first and second chip-sized wafer level packaged devices each including: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including a device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface, at least one packaging layer formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface, a first ball grid array formed over said surface of said at least one packaging layer and being electrically coupled to said first bond pads, a second ball grid array formed over said second surface of said die and being electrically coupled to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer, wherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer, and a compliant electrophoretic coating layer underlying at least one of said first or second ball grid arrays; and said first ball grid array of said first device being coupled to said second ball grid array of said second device. ### Claim 37 (depends on 36) Stacked chip-sized, wafer level packaged devices according to claim 36 and wherein said at least one packaging layer contains silicon. ### Claim 38 (depends on 36) Stacked chip-sized, wafer level packaged devices according to claim 36 and wherein said compliant electrophoretic coating layer provides alpha-particle shielding between the at least one of said first or second ball grid arrays and said device. ### Claim 39 (depends on 36) Stacked chip-sized, wafer level packaged devices according to claim 36 and wherein said device is a DRAM device. ### Claim 40 A chip-sized wafer level packaged device comprising: a die severed being a portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface; a packaging layer formed over said first surface and remote from said second surface of said die, said packaging layer comprising a material having thermal expansion characteristics similar to those of said die, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface; a plurality of first interconnects formed over said surface of said packaging layer and being electrically connected to said first bond pads; and a plurality of second interconnects formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer, wherein the die has a thickness extending from the first surface to the second surface, and wherein the plurality of first interconnects is aligned with the plurality of the second interconnects in a direction of the thickness of the die. ### Claim 41 (depends on 40) A chip-sized wafer level packaged device according to claim 40 and wherein at least one of said plurality of said first interconnects or said plurality of said second interconnects comprise ACF attachable interconnects. ### Claim 42 (depends on 41) A chip-sized wafer level packaged device according to claim 41 and wherein said ACF attachable interconnects are formed of copper. ### Claim 43 (depends on 40) A chip-sized wafer level packaged device according to claim 40 and also comprising: a printed circuit board including interconnects; and a conductive film bonding said interconnects of said printed circuit board to at least one of said plurality of first interconnects or said plurality of second interconnects. ### Claim 44 (depends on 43) A chip-sized wafer level packaged device according to claim 43 and wherein said conductive film comprises an anisotropic conductive film. ### Claim 45 (depends on 40) A chip-sized wafer level packaged device according to claim 40, wherein said semiconductor wafer contains at least one of silicon or Gallium Arsenide. ### Claim 46 (depends on 40) A chip-sized wafer level packaged device according to claim 40, wherein said packaging layer is adhered to said die by an adhesive, said adhesive having thermal expansion characteristics similar to those of said packaging layer. ### Claim 47 (depends on 40) A chip-sized wafer level packaged device according to claim 40 and wherein said packaging layer comprises silicon. ### Claim 48 (depends on 40) A chip-sized wafer level packaged device according to claim 40 and wherein said device includes a memory device. ### Claim 49 (depends on 40) A chip-sized wafer level packaged device according to claim 40, wherein said packaging layer includes a first packaging layer, said packaged device further comprising: a first compliant layer provided on said first packaging layer and underlying said plurality of first interconnects; a second packaging layer formed over said second surface of said die, wherein said plurality of second interconnects are formed over said second packaging layer; and a second compliant layer provided in said second packaging layer and underlying said plurality of second interconnects. ### Claim 50 (depends on 49) A chip-sized wafer level packaged device according to claim 49, wherein said compliant layers comprise electrophoretic material for providing alpha-particle shielding between said first and second interconnects and said device. ### Claim 51 (depends on 40) A chip-sized, wafer level packaged device according to claim 40, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. ### Claim 52 A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface; at least one packaging layer containing silicon and formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface; a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads; and a second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer, wherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer. ### Claim 53 (depends on 52) A chip-sized, wafer level packaged device according to claim 52 and wherein said at least one packaging layer comprises a plurality of packaging layers. ### Claim 54 (depends on 53) A chip-sized, wafer level packaged device according to claim 53 and wherein said plurality of packaging layers are disposed on the same side of said die. ### Claim 55 (depends on 52) A chip-sized wafer level packaged device according to claim 52 and wherein said device is a DRAM device. ### Claim 56 (depends on 52) A chip-sized wafer level packaged device according to claim 52 and also comprising a first compliant layer, formed over said packaging layer and underlying said first ball grid array. ### Claim 57 (depends on 56) A chip-sized wafer level packaged device according to claim 56, wherein said first conductors are formed over said first compliant layer and are underlying said first ball grid array. ### Claim 58 (depends on 56) A chip-sized wafer level packaged device according to claim 56 and wherein said first compliant layer includes at least one of silicone or a polymeric dielectric material. ### Claim 59 (depends on 58) A chip-sized wafer level packaged device according to claim 58 and wherein said polymeric material comprises a polyimide. ### Claim 60 (depends on 56) A chip-sized wafer level packaged device according to claim 56 and also comprising a second compliant layer, formed over said first surface of said die and underlying said second ball grid array. ### Claim 61 (depends on 60) A chip-sized wafer level packaged device according to claim 60, wherein said second conductors are formed over said second compliant layer and are underlying said second ball grid array. ### Claim 62 (depends on 60) A chip-sized wafer level packaged device according to claim 60 and wherein said first compliant layer includes at least one of silicone or a polymeric dielectric material. ### Claim 63 (depends on 62) A chip-sized wafer level packaged device according to claim 62 and wherein said polymeric material comprises a polyimide. ### Claim 64 (depends on 52) A chip-sized wafer level packaged device according to claim 52 and wherein alpha-particle shielding is provided between at least one of said first or second ball grid arrays and said device. ### Claim 65 (depends on 52) A chip-sized wafer level packaged device according to claim 52, wherein said at least one packaging layer includes a first packaging layer, said packaged device further comprising: a second packaging layer formed over said second surface of said die, wherein said first ball grid array is formed on said first packaging layer and said second ball grid array is formed on said second packaging layer. ### Claim 66 (depends on 65) A chip-sized wafer level packaged device according to claim 65, further comprising: first compliant layer formed on said first packaging layer and underlying said first ball grid array; and second compliant layer formed on said second packaging layer and underlying said second ball grid array. ### Claim 67 (depends on 66) A chip-sized wafer level packaged device according to claim 66, wherein at least one of said compliant layers provides alpha-particle shielding between at least one of said first or second ball grid arrays and said device. ### Claim 68 (depends on 66) A chip-sized wafer level packaged device according to claim 66, wherein at least one of said compliant layers comprises a layer of an electrophoretic material. ### Claim 69 (depends on 52) A chip-sized, wafer level packaged device according to claim 52, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. ### Claim 70 A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface; at least one packaging layer formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface; a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads; a second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer; and a compliant electrophoretic coating layer underlying at least one of said first or second ball grid arrays, wherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer. ### Claim 71 (depends on 70) A chip-sized wafer level packaged device according to claim 70 and wherein said at least one packaging layer contains silicon. ### Claim 72 (depends on 70) A chip-sized wafer level packaged device according to claim 70 and wherein said compliant electrophoretic coating layer provides alpha-particle shielding between the at least one of said first or second ball grid arrays and said device. ### Claim 73 (depends on 70) A chip-sized wafer level packaged device according to claim 70 and wherein said device is a DRAM device. ### Claim 74 (depends on 70) A chip-sized, wafer level packaged device according to claim 70 and wherein said at least one packaging layer comprises a plurality of packaging layers. ### Claim 75 (depends on 74) A chip-sized, wafer level packaged device according to claim 74 and wherein said plurality of packaging layers are disposed on the same side of said die. ### Claim 76 (depends on 70) A chip-sized wafer level packaged device according to claim 70, and also comprising metal connections formed over said compliant electrophoretic coating layer and underlying the at least one of said first or second ball grid arrays, said metal connections providing electrical contact between the at least one of said first or second ball grid arrays and said device. ### Claim 77 (depends on 70) A chip-sized wafer level packaged device according to claim 70 and wherein said compliant electrophoretic coating layer includes at least one of silicone or a polymeric dielectric material. ### Claim 78 (depends on 77) A chip-sized wafer level packaged device according to claim 77 and wherein said polymeric material comprises a polyimide. ### Claim 79 (depends on 70) A chip-sized wafer level packaged device according to claim 70, wherein said at least one packaging layer includes a first packaging layer, said packaged device further comprising: a second packaging layer formed over said second surface of said die, wherein said first ball grid array is formed on said first packaging layer and said second ball grid array is formed on said second packaging layer. ### Claim 80 (depends on 79) A chip-sized wafer level packaged device according to claim 79, wherein said compliant electrophoretic coating layer comprises: first compliant electrophoretic coating layer formed on said first packaging layer and underlying said first ball grid array; and second compliant electrophoretic coating layer formed on said second packaging layer and underlying said second ball grid array. ### Claim 81 (depends on 80) A chip-sized wafer level packaged device according to claim 80, wherein said first and second electrophoretic coating layers provides alpha-particle shielding between said first and second ball grid arrays and said device. ### Claim 82 (depends on 70) A chip-sized, wafer level packaged device according to claim 70, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. ### Claim 83 A chip-sized wafer level packaged device comprising: a die severed being a portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface; a packaging layer formed over said first surface and remote from said second surface of said die, said packaging layer comprising a material having thermal expansion characteristics similar to those of said die, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface; a plurality of first interconnects formed over said surface of said packaging layer and being electrically connected to said first bond pads; and a plurality of second interconnects formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer, wherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer. ### Claim 84 (depends on 83) A chip-sized wafer level packaged device according to claim 83 and wherein at least one of said plurality of said first interconnects or said plurality of said second interconnects comprise ACF attachable interconnects. ### Claim 85 (depends on 84) A chip-sized wafer level packaged device according to claim 84 and wherein said ACF attachable interconnects are formed of copper. ### Claim 86 (depends on 83) A chip-sized wafer level packaged device according to claim 83 and also comprising: a printed circuit board including interconnects; and a conductive film bonding said interconnects of said printed circuit board to at least one of said plurality of first interconnects or said plurality of second interconnects. ### Claim 87 (depends on 86) A chip-sized wafer level packaged device according to claim 86 and wherein said conductive film comprises an anisotropic conductive film. ### Claim 88 (depends on 83) A chip-sized wafer level packaged device according to claim 83, wherein said semiconductor wafer contains at least one of silicon or Gallium Arsenide. ### Claim 89 (depends on 83) A chip-sized wafer level packaged device according to claim 83, wherein said packaging layer is adhered to said die by an adhesive, said adhesive having thermal expansion characteristics similar to those of said packaging layer. ### Claim 90 (depends on 83) A chip-sized wafer level packaged device according to claim 83 and wherein said packaging layer comprises silicon. ### Claim 91 (depends on 83) A chip-sized wafer level packaged device according to claim 83 and wherein said device includes a memory device. ### Claim 92 (depends on 83) A chip-sized wafer level packaged device according to claim 83, wherein said packaging layer includes a first packaging layer, said packaged device further comprising: a first compliant layer provided on said first packaging layer and underlying said plurality of first interconnects; a second packaging layer formed over said second surface of said die, wherein said plurality of second interconnects are formed over said second packaging layer; and a second compliant layer provided in said second packaging layer and underlying said plurality of second interconnects. ### Claim 93 (depends on 92) A chip-sized wafer level packaged device according to claim 92, wherein said compliant layers comprise electrophoretic material for providing alpha-particle shielding between said first and second interconnects and said device. ### Claim 94 (depends on 83) A chip-sized, wafer level packaged device according to claim 83, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors.