# US 8,569,873 B2 · Mitigation of plating stub resonance by controlling surface roughness

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- Number: US 8,569,873 B2
- Document ID: US8569873B2
- Status: Granted
- Kind: B2
- Application number: 13/272,930
- Filed: 2011-10-13
- Published: 2012-02-09
- Granted: 2013-10-29
- Earliest claimed: 2008-10-21
- Assignees: International Business Machines Corporation
- Applicants: Bhyrav M. Mutnury; Moises Cases; Tae Hong Kim; Nanju Na
- Inventors: Bhyrav M. Mutnury; Moises Cases; Tae Hong Kim; Nanju Na
- Web page: https://patentgrep.com/patent/US8569873B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 1/025: {Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance (H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H10W44/20)}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H05K 3/242: {characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated}
- H05K 3/382: {by special treatment of the metal}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49124: On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T 29/49128: Assembling formed circuit to base
- Y10T 29/49147: Assembling terminal to base
- Y10T 29/49155: Manufacturing circuit on or in base
- Y10T 156/10: Methods of surface bonding and/or assembly therefor
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

## Claims

### Claim 1

A chip package, comprising:
a substrate of a printed circuit board;
a signal interconnect disposed on an exterior surface of the substrate;
a signal trace extending along the exterior surface of the substrate from near a chip mounting location to the signal interconnect; and
a plating stub extending from the signal interconnect to a periphery of the substrate along the exterior surface of the substrate, the plating stub including a roughened exterior surface having an average surface deviation of between about five to fifteen micrometers.

### Claim 2 (depends on 1)

The chip package of claim 1, wherein the average surface deviation is less than about half the thickness of the plating stub.

### Claim 3 (depends on 1)

The chip package of claim 1, further comprising:
a chip mounted on the substrate at the chip mounting location.

### Claim 4 (depends on 3)

The chip package of claim 3, further comprising:
a bond wire connecting a bond pad on the chip to the signal trace.

### Claim 5 (depends on 1)

The chip package of claim 1, wherein the signal trace extends outwardly from a centrally located chip mounting location.

### Claim 6 (depends on 1)

The chip package of claim 1, further comprising:
a ball grid array, wherein the signal interconnect is electrically connected to a ball of the ball grid array.

### Claim 7 (depends on 1)

The chip package of claim 1, wherein the roughened exterior surface has a plurality of alternating projections and valleys along the exterior surface of the plating stub.

### Claim 8 (depends on 7)

The chip package of claim 7, wherein the alternating projections form a plurality of parallel ridges.

### Claim 9 (depends on 1)

The chip package of claim 1, wherein the roughened exterior surface has an average surface deviation of no more than about half the thickness of the as-formed plating stub.

### Claim 10 (depends on 1)

The chip package of claim 1, wherein the roughened exterior surface has a roughness profile with peaks and valleys distributed in one dimension.

### Claim 11 (depends on 1)

The chip package of claim 1, wherein the roughened exterior surface has a roughness profile with peaks and valleys distributed in two dimensions.

### Claim 12 (depends on 1)

The chip package of claim 1, wherein the roughened exterior surface has generally triangular peaks and valleys.

### Claim 13 (depends on 1)

The chip package of claim 1, wherein the roughened exterior surface has a uniform surface pattern.

### Claim 14 (depends on 1)

The chip package of claim 1, wherein the roughened exterior surface has a random surface pattern.