# US 8,569,868 B2 · Device having and method for forming fins with multiple widths

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- Number: US 8,569,868 B2
- Document ID: US8569868B2
- Status: Granted
- Kind: B2
- Application number: 13/552,296
- Filed: 2012-07-18
- Published: 2012-11-08
- Granted: 2013-10-29
- Earliest claimed: 2009-11-09
- Assignees: International Business Machines Corporation
- Applicants: Kangguo Cheng; Bruce B. Doris; Steven J. Holmes; Xuefeng Hua; Ying Zhang
- Inventors: Kangguo Cheng; Bruce B. Doris; Steven J. Holmes; Xuefeng Hua; Ying Zhang
- Web page: https://patentgrep.com/patent/US8569868B2

## CPC

- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10P 76/40: of masks comprising inorganic materials
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

## Claims

### Claim 1

A structure for a semiconductor device, comprising:
a first feature and a second feature formed simultaneously in a single etch process from a same monolithic substrate layer, the first feature and the second feature being integrally, physically and directly connected to each other; and
the first feature having a width dimension of less than a minimum feature size achievable by lithography,
the second feature having a width dimension of at least equal to a minimum feature size achievable by lithography.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the semiconductor device is a transistor device and wherein at least one of the first feature or the second feature is a fin of the transistor device.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the first and second features are in a metal layer of the semiconductor device.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the first and second features are in an interlevel dielectric layer of the semiconductor device.

### Claim 5 (depends on 1)

The structure of claim 1, wherein the first feature is a bar feature.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the second feature is a ring feature.

### Claim 7 (depends on 1)

The structure of claim 1, wherein the first feature is a ring feature.

### Claim 8 (depends on 1)

The structure of claim 1, wherein the second feature is a bar feature.

### Claim 9

A structure for a semiconductor device, comprising:
a first feature and a second feature formed simultaneously in a single etch process from a same monolithic substrate layer, the first feature and the second feature being integrally and continuously connected to each other; and
the first feature having a width dimension of less than a minimum feature size achievable by lithography,
the second feature having a width dimension of at least equal to a minimum feature size achievable by lithography,
wherein the first and second features are in a metal layer of the semiconductor device.

### Claim 10

A structure for a semiconductor device, comprising:
a first feature and a second feature formed simultaneously in a single etch process from a same monolithic substrate layer, the first feature and the second feature being integrally and continuously connected to each other; and
the first feature having a width dimension of less than a minimum feature size achievable by lithography,
the second feature having a width dimension of at least equal to a minimum feature size achievable by lithography,
wherein the first and second features are in an interlevel dielectric layer of the semiconductor device.