# US 8,569,867 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,867 B2 - Document ID: US8569867B2 - Status: Granted - Kind: B2 - Application number: 13/364,716 - Filed: 2012-02-02 - Published: 2012-12-20 - Granted: 2013-10-29 - Earliest claimed: 2011-06-15 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Satoshi Inaba - Inventors: Satoshi Inaba - Web page: https://patentgrep.com/patent/US8569867B2 ## CPC - H10D 18/251: {Lateral thyristors} - H10D 18/031: {of lateral or planar thyristors} - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract According to one embodiment, a semiconductor device that has a rectification element includes a semiconductor substrate, a first well region of a first conductivity type formed on the semiconductor substrate, a second well region of a second conductivity type formed on the semiconductor substrate, and a plurality of fins arranged over the first well region and the second well region at a first pitch in the same direction. In the semiconductor device, the rectification element includes a cathode region, an anode region, a well contact region, and a trigger region that are configured using fins. These regions are connected to each wiring portion to form a PNP-type bipolar transistor and an NPN-type bipolar transistor. ## Claims ### Claim 1 A semiconductor device that has a rectification element, comprising: a semiconductor substrate; a first well region of a first conductivity type formed on the semiconductor substrate; a second well region of a second conductivity type formed on the semiconductor substrate; and a plurality of fins arranged over the first well region and the second well region at a first pitch in the same direction, wherein the first well region and the second well region are arranged to come in contact with each other in a direction along a short side of the fin to form a well region boundary parallel to a long side of the fin, a first pair of the fins are positioned so as to interpose the well region boundary therebetween, one fin of the first pair being a cathode region with a second conductivity type impurity diffusion layer region positioned in the first well region, and another fin of the first pair being an anode region with a first conductivity type impurity diffusion layer region positioned in the second well region, a second pair of the fins are positioned so as to interpose the first pair therebetween, one fin of the second pair being a well contact region with a first conductivity type impurity diffusion layer region positioned in the first well region, and another fin of the second pair being a trigger region with a second conductivity type impurity diffusion layer region positioned in the second well region, the rectification element includes the cathode region, the anode region, the well contact region, and the trigger region, each of the cathode region, the anode region, the well contact region, and the trigger region is connected to each wiring portion to form a PNP-type bipolar transistor and an NPN-type bipolar transistor, and the first well region is positioned at the outermost circumference of the semiconductor substrate, and the semiconductor device further includes an outermost circumferential fin positioned to be closer to the outer circumference from the well contact region, the outermost circumferential fin having a first conductivity type impurity diffusion layer region, and being in an electrically floating state. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the outermost circumferential fin has a shape that is different from a shape of the fins. ### Claim 3 (depends on 1) The semiconductor device of claim 1, further comprising: at least two outermost circumferential fins that are adjacent to each other in a direction along the short side of the fin. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein each of the cathode region, the anode region, the well contact region, and the trigger region is connected to each wiring portion by a contact region, and the contacts are arranged in a checker shape. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the wiring portions are arranged at a second pitch in a direction along the short side of the fin. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein each of the well contact region, the cathode region, the anode region, and the trigger region is configured using at least two fins to be adjacent to each other in a direction along the short side of the fin. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein each of the cathode region, the anode region, the well contact region, and the trigger region is connected to each wiring portion by a contact region, and the contacts are arranged in a checker shape. ### Claim 8 (depends on 6) The semiconductor device of claim 6, wherein the wiring portions are arranged at a second pitch in a direction along the short side of the fin. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the second pitch is larger than the first pitch. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the fins have rectangular ring shapes. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the first well region is positioned at the outermost circumference of the semiconductor substrate, and the semiconductor device further includes an outermost circumferential fin positioned to be closer to the outer circumference from the well contact region, the outermost circumferential fin having a rectangular ring shape and a first conductivity type impurity diffusion layer region, and being in an electrically floating state. ### Claim 12 A semiconductor device that has a rectification element, comprising: a semiconductor substrate; a first well region of a first conductivity type formed on the semiconductor substrate; a second well region of a second conductivity type formed on the semiconductor substrate; and a plurality of fins that have rectangular ring shapes and are arranged over the first well region and the second well region at a first pitch in the same direction, wherein the first well region and the second well region are arranged to be in contact with each other in a direction along a short side of the fin to form a well region boundary parallel to a long side of the fin, a first pair of the fins are positioned so as to interpose the well region boundary therebetween, one fin of the first pair being a cathode region with second conductivity type impurity diffusion layer region positioned in the first well region, and another fin of the first pair being an anode region with a first conductivity type impurity diffusion layer region positioned in the second well region, a second pair of the fins are positioned so as to interpose the first pair therebetween, one fin of the second pair being a well contact region with a first conductivity type impurity diffusion layer region positioned in the first well region, and another fin of the second pair being a trigger region with a second conductivity type impurity diffusion layer region positioned in the second well region, the rectification element includes the cathode region, the anode region, the well contact region, and the trigger region, and each of the cathode region, the anode region, the well contact region, and the trigger region is connected to each wiring portion to form a PNP-type bipolar transistor and an NPN-type bipolar transistor. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the first well region is positioned at the outermost circumference of the semiconductor substrate, and the semiconductor device further includes an outermost circumferential fin positioned to be closer to the outer circumference from the well contact region, the outermost circumferential fin having a rectangular ring shape and a first conductivity type impurity diffusion layer region, and being in an electrically floating state. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein each of the cathode region, the anode region, the well contact region, and the trigger region is connected to each wiring portion by a contact region, and the contacts are arranged in a checker shape. ### Claim 15 (depends on 13) The semiconductor device of claim 13, wherein the outermost circumferential fin has a shape that is different from a shape of the fins. ### Claim 16 (depends on 13) The semiconductor device of claim 13, wherein the outermost circumferential fin includes a dummy contact region. ### Claim 17 A semiconductor device that has a rectification element, comprising: a semiconductor substrate; a first well region of a first conductivity type formed on the semiconductor substrate; a second well region of a second conductivity type formed on the semiconductor substrate; and a plurality of fins arranged over the first well region and the second well region at a first pitch in the same direction, wherein the first well region and the second well region are arranged to come in contact with each other in a direction along a short side of the fin to form a well region boundary parallel to a long side of the fin, a first pair of the fins are positioned so as to interpose the well region boundary therebetween, one fin of the first pair being a cathode region with a second conductivity type impurity diffusion layer region positioned in the first well region, and another fin of the first pair being an anode region with a first conductivity type impurity diffusion layer region positioned in the second well region, a second pair of the fins are positioned so as to interpose the first pair therebetween, one fin of the second pair being a well contact region with a first conductivity type impurity diffusion layer region positioned in the first well region, and another fin of the second pair being a trigger region with a second conductivity type impurity diffusion layer region positioned in the second well region, the rectification element includes the cathode region, the anode region, the well contact region, and the trigger region, each of the cathode region, the anode region, the well contact region, and the trigger region is connected to each wiring portion to form a PNP-type bipolar transistor and an NPN-type bipolar transistor, and the wiring portions are arranged at a second pitch in a direction along the short side of the fin. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the first well region is positioned at the outermost circumference of the semiconductor substrate, and the semiconductor device further includes an outermost circumferential fin positioned to be closer to the outer circumference from the well contact region, the outermost circumferential fin having a first conductivity type impurity diffusion layer region, and being in an electrically floating state. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein the outermost circumferential fin has a shape that is different from a shape of the fins. ### Claim 20 (depends on 18) The semiconductor device of claim 18, wherein a portion of the outermost circumferential fin is covered by the wiring portion.