# US 8,569,866 B2 · Hybrid-integrated lateral bipolar transistor and CMOS transistor and method for manufacturing the same

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- Number: US 8,569,866 B2
- Document ID: US8569866B2
- Status: Granted
- Kind: B2
- Application number: 12/808,874
- Filed: 2008-12-19
- Published: 2011-11-03
- Granted: 2013-10-29
- Earliest claimed: 2007-12-20
- Assignees: Asahi Kasei Microdevices Corporation
- Applicants: Tomislav Suligoj; Marko Koricic; Hidenori Mochizuki; Soichi Morita
- Inventors: Tomislav Suligoj; Marko Koricic; Hidenori Mochizuki; Soichi Morita
- Web page: https://patentgrep.com/patent/US8569866B2

## CPC

- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)}
- H10D 10/60: Lateral BJTs
- H10D 62/134: {of lateral BJTs}
- H10D 62/184: {of lateral BJTs}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 30/225: {of a molecular ion, e.g. decaborane}
- H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.

## Claims

### Claim 1

A semiconductor device in which a lateral bipolar transistor and a CMOS transistor are hybrid-integrated,
the lateral bipolar transistor including:
an open region opened in a device isolating oxide film surrounding an active region;
a polysilicon film formed on the open region and having such a thickness as to expose the active region out of the polysilicon film;
an intrinsic base region of the lateral bipolar transistor; and
a protective film covering at least a part of a peripheral surface of the active region exposed by opening the open region in the device isolating oxide film and having a thickness of 6 to 8 angstrom;
wherein the protective film is located on between the polysilicon film and the intrinsic base region.

### Claim 2

A semiconductor device in which a lateral bipolar transistor and a CMOS transistor are hybrid-integrated,
the lateral bipolar transistor including:
an open region opened in a device isolating oxide film surrounding an active region;
a polysilicon film formed on the open region and having such a thickness as to expose the active region out of the polysilicon film;
an intrinsic base region of the lateral bipolar transistor; and
a protective film covering at least part of a peripheral surface of the active region exposed by opening the open region in the device isolating oxide film and having a thickness of 6 to 8 angstrom;
a collector diffusion layer formed in the active region; and
a collector electrode directly connected to the collector diffusion layer region,
wherein the protective film is located on between the polysilicon film and the intrinsic base region.

### Claim 3

A semiconductor device comprising a lateral bipolar transistor,
the lateral bipolar transistor including:
a substrate including a first conductive layer;
an active region located on the first conductive layer and having such a shape as to protrude from the first conductive layer and have an upper surface and at least one side surface in contact with the upper surface;
an open region opened in a device isolating oxide film surrounding the active region;
a polysilicon film formed on the open region;
an emitter region solid-phase diffused from the polysilicon film; and
a dummy gate polysilicon formed in the device isolating oxide film and having an upper surface which is located above the upper surface of the active region,
wherein an upper surface of the active region is located above an upper surface of the emitter region.

### Claim 4 (depends on 3)

The semiconductor device according claim 3 further comprising a CMOS transistor integrated on the substrate.

### Claim 5

A method for manufacturing a semiconductor device in which a lateral bipolar transistor and a CMOS transistor are hybrid-integrated, the method comprising the steps of:
forming an extrinsic base region for externally connecting a base region of an active region of the lateral bipolar transistor, following a step of at least one time of ion implantation in which an impurity is implanted with the gate electrode of the CMOS transistor used as a mask;
forming an open region around the active region by removing a predetermined portion of a device isolating oxide film surrounding the active region;
forming an intrinsic base region of the lateral bipolar transistor by implanting ions in a region of a side surface of the active region exposed by the formation of the open region partially overlapping with the extrinsic base region;
forming a protective film for protecting the active region during etching in a subsequent step on a surface of the active region;
forming an impurity-containing polysilicon film in a region including the active region in which the protective film is formed and the open region in the protective film formation step;
etching away the polysilicon film by a predetermined thickness; and
forming an emitter diffusion layer region and a collector diffusion layer region by solid-phase diffusing an impurity from the impurity-containing polysilicon film left after etching in the polysilicon etching step.

### Claim 6 (depends on 5)

The method for manufacturing a semiconductor device according to claim 5, wherein the protective film is an oxide film having such a thickness as to prevent the active region of the lateral bipolar transistor from being etched in the polysilicon etching step.

### Claim 7

A method for manufacturing a semiconductor device in which a lateral bipolar transistor and a CMOS transistor are hybrid-integrated, the method comprising the steps of:
forming an extrinsic base region for externally connecting a base region of an active region of the lateral bipolar transistor, following a step of at least one time of conductive film formation in which an impurity is implanted with the gate electrode of the CMOS transistor used as a mask;
forming an open region around the active region by removing a predetermined portion of the device isolating oxide film surrounding the active region;
forming an intrinsic base region of the lateral bipolar transistor by implanting ions in a region of a side surface of the active region exposed by the formation of the open region partially overlapping with the extrinsic base region;
forming a protective film for protecting the active region during etching in a subsequent step on a surface of the active region;
forming an impurity-containing polysilicon film in a region including the active region in which the protective film is formed and the open region in the protective film formation step;
etching away the polysilicon film by a predetermined thickness;
forming an emitter diffusion layer region by solid-phase diffusing an impurity from the impurity-containing polysilicon film left after etching in the polysilicon etching step;
forming a collector diffusion region in the active layer; and
forming an electrode directly connected to the collector diffusion layer region.

### Claim 8 (depends on 7)

The method for manufacturing a semiconductor device according to claim 7, wherein the protective film is an oxide film having such a thickness as to prevent the active region of the lateral bipolar transistor from being etched in the polysilicon etching step.

### Claim 9

A method for manufacturing a semiconductor device including a lateral bipolar transistor, wherein a step of manufacturing the lateral bipolar transistor includes the steps of:
forming an active region having such a shape as to protrude from a first conductive layer and have an upper surface and at least one side surface in contact with the upper surface on the first conductive layer serving as a substrate;
opening an open region in the device isolating oxide film surrounding the active region;
forming a polysilicon film on the open region;
forming an emitter region by solid-phase diffusing the emitter region from the polysilicon film; and
forming a dummy gate polysilicon in the device isolating oxide film,
and the shape of the emitter region solid-phase diffused from the polysilicon film is controlled by the dummy gate polysilicon.