# US 8,569,865 B2 · Integrated circuit and production method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,865 B2 - Document ID: US8569865B2 - Status: Granted - Kind: B2 - Application number: 13/424,792 - Filed: 2012-03-20 - Published: 2012-07-12 - Granted: 2013-10-29 - Earliest claimed: 2006-03-22 - Assignees: Infineon Technologies AG - Applicants: Matthias Stecher - Inventors: Matthias Stecher - Web page: https://patentgrep.com/patent/US8569865B2 ## CPC - H10W 10/30: Isolation regions comprising PN junctions - H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10W 10/031: {of isolation regions comprising PN junctions} - H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials} - H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials - H10D 30/665: {having edge termination structures} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate. ## Claims ### Claim 1 An integrated circuit comprising: a semiconductor substrate of a first conductivity type; a first semiconductor well and a second semiconductor well, each of a second conductivity type formed adjacently to one another and insulated from one another in the same semiconductor substrate, wherein surfaces of the first semiconductor well, and the second semiconductor well define a main area; electrode patterns of a power transistor including a reverse-current injecting electrode pattern of the power transistor are formed in the first semiconductor well; an insulating material placed in a deep trench structure extending from the main area into the semiconductor substrate for providing insulation between the first semiconductor well and the second semiconductor well, the deep trench structure comprising two intermediate trenches extending into the semiconductor substrate, wherein the two intermediate trenches are lined with an insulating material and filled with a material comprised of polysilicon; a third semiconductor well of the first conductivity type extending from the main area into the first semiconductor well such that the third semiconductor well is provided between the main area and the first semiconductor well, the third semiconductor well directly connectable to ground potential or to a potential which is more negative compared with the ground potential; and at least one reverse-current complex formed between the reverse-current injecting electrode pattern of the power transistor and the insulating material, said at least one reverse current complex having in each case a reverse-current-absorbing semiconductor zone of the second conductivity type which is located in the third semiconductor well and connected to the semiconductor substrate via a substrate connection extending through the deep trench structure between the insulating material of the two intermediate trenches. ### Claim 2 (depends on 1) The integrated circuit of claim 1, comprising: electrode patterns of a power transistor are formed in the first semiconductor well. ### Claim 3 (depends on 2) The integrated circuit of claim 2, comprising: semiconductor zones formed in the second semiconductor well and insulation between the first and second semiconductor well is formed by an insulating material placed in at least one deep trench extending from the main area into the substrate. ### Claim 4 (depends on 3) The integrated circuit of claim 3, comprising: at least one reverse-current complex, formed between an electrode pattern injecting a reverse current of the power transistor and the trench insulation, which in each case has the reverse-current-injection-absorbing semiconductor zone, located in the third semiconductor well formed in the first semiconductor well. ### Claim 5 (depends on 3) The integrated circuit of claim 3, comprising: wherein the third semiconductor well extends from the main area into the first semiconductor well and is connected to ground potential or to a potential which is more negative compared with the former. ### Claim 6 (depends on 1) The integrated circuit of claim 1, comprising wherein the substrate is formed of a first conduction type and the first semiconductor and the second semiconductor is formed of a second conduction type. ### Claim 7 (depends on 1) The integrated circuit of claim 1, comprising wherein a number of distributed reverse-current complexes are formed in the first semiconductor well. ### Claim 8 (depends on 7) The integrated circuit of claim 7, comprising where the reverse-current complexes are short circuited with a substrate contact ring surrounding the reverse-current complexes. ### Claim 9 (depends on 1) The integrated circuit of claim 1, comprising wherein a buried layer is formed between the substrate and at least the first semiconductor well and is connected to the reverse-current-injecting pattern of the power transistor. ### Claim 10 (depends on 9) The integrated circuit of claim 9, comprising wherein a further buried layer is formed between the substrate and the second semiconductor well. ### Claim 11 (depends on 1) The integrated circuit of claim 1, wherein the electrode patterns of a power transistor form a DMOS, HVMOS, MedV-MOS, LowV-MOS transistor or a bipolar transistor. ### Claim 12 An integrated circuit having a semiconductor arrangement comprising: a first semiconductor well and a second semiconductor well, both of which are formed with the same second conduction type adjacently to one another and insulated from one another in a semiconductor substrate of the first conduction type and which define a main area of the semiconductor arrangement, wherein electrode patterns of a power transistor including a reverse current injecting electrode pattern are formed in the first semiconductor well, and semiconductor zones having conduction types differing from one another are formed in the second semiconductor well, and an insulation between the first semiconductor well and the second semiconductor well is formed by an insulating material placed in a deep trench structure extending from the main area into the semiconductor substrate, the deep trench structure comprising two intermediate trenches extending into the semiconductor substrate, wherein the two intermediate trenches are lined with an insulating material and filled with a material comprised of polysilicon; and at least one reverse-current complex, formed between the reverse-current injecting electrode pattern of the power transistor and a trench insulation, the at least one reverse-current complex having in each case a reverse-current-absorbing semiconductor zone of the second conduction type located in a third semiconductor well of the first conduction type formed in the first semiconductor well; wherein the third semiconductor well extends from the main area into the first semiconductor well and is directly connectable to ground potential or to a potential which is more negative compared with the ground potential, and the reverse-current-absorbing semiconductor zone is connected to the semiconductor substrate via a substrate connection extending through the deep trench structure, the deep trench structure comprising two intermediate trenches extending into the semiconductor substrate, wherein the two intermediate trenches are lined with an insulating material and filled with a material comprised of polysilicon, wherein a buried layer of the second conduction type is formed between the substrate and at least the first semiconductor well and is there connected to the reverse-current-injecting electrode pattern of the power transistor, and wherein a further buried layer of the second conduction type is formed between the substrate and the second semiconductor well. ### Claim 13 (depends on 12) The integrated circuit of claim 12, comprising wherein the first conduction type is the p-type of conduction and the second conduction type is the n-type of conduction. ### Claim 14 (depends on 12) The integrated circuit of claim 12, comprising wherein a number of distributed reverse-current complexes are formed in the first semiconductor well. ### Claim 15 (depends on 14) The integrated circuit of claim 14, comprising wherein the reverse-current complexes are short circuited with a substrate contact ring surrounding the reverse-current complexes. ### Claim 16 (depends on 12) The integrated circuit of claim 12, comprising wherein a buried layer of the second conduction type is formed between the substrate and at least the first semiconductor well and is there connected to the reverse-current-injecting pattern of the power transistor. ### Claim 17 (depends on 16) The integrated circuit of claim 16, comprising wherein a further buried layer of the second conduction type is formed between the substrate and the second semiconductor well. ### Claim 18 (depends on 12) The semiconductor arrangement of claim 12, comprising wherein the power transistor is a DMOS, HVMOS, MedV-MOS, LowV-MOS transistor or a bipolar transistor.