# US 8,569,860 B2 · Semiconductor devices having line type active regions and methods of fabricating the same

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- Number: US 8,569,860 B2
- Document ID: US8569860B2
- Status: Granted
- Kind: B2
- Application number: 12/905,614
- Filed: 2010-10-15
- Published: 2011-02-10
- Granted: 2013-10-29
- Earliest claimed: 2005-03-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Kye-Hee Yeom
- Inventors: Kye-Hee Yeom
- Web page: https://patentgrep.com/patent/US8569860B2

## CPC

- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 64/027: {by etching at gate locations}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B 12/05: {Making the transistor}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a planar type device isolation gate electrode, and a width of the planar type device isolation gate electrode greater than a width of the device gate electrode.

## Claims

### Claim 1

A semiconductor device, comprising:
a device isolation layer which defines line type active regions in a semiconductor substrate; and
at least four gate electrodes of substantially uniform width which are disposed over the semiconductor substrate to be parallel to each other and wherein the at least four gate electrodes completely overlap and intersect one of the line type active regions,
wherein the gate electrodes include both a device gate electrode and planar type device isolation gate electrode,
wherein the widths of the gate electrodes are constant in length thereof, and
wherein a width of the planar type device isolation gate electrode is greater than a width of the device gate electrode.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the at least four gate electrodes include two planar type device isolation gate electrodes and two device gate electrode.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the two device gate electrodes are planar type device gate electrode.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein the two device gate electrodes are recessed device gate electrode.

### Claim 5

A semiconductor device, comprising:
a device isolation layer which defines line type active regions in a semiconductor substrate; and
gate electrodes of substantially uniform width which are disposed over the semiconductor substrate to be parallel to each other and intersect the line type active regions,
wherein the gate electrodes include both a device gate electrode and a planar type device isolation gate electrodes,
wherein a width of the planar type device isolation gate electrode is greater than a width of the device gate electrode, and
wherein the width of the planar type device isolation gate electrode is on a same horizontal level with the width of the device gate electrode.

### Claim 6

A semiconductor device, comprising:
device isolation regions defining active regions in a semiconductor substrate; and
at least four gate electrodes of substantially uniform width having at least two device gate electrodes and at least two device isolation gate electrodes,
wherein the at least four gate electrodes completely overlap and intersect both one of the device isolation regions and one of the active regions, widths of the device isolation gate electrodes are greater than widths of the device gate electrodes at a same horizontal level being in parallel to a surface of the semiconductor substrate.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, the device isolation regions and the active regions are parallel with each other.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the at least four gate electrodes diagonally intersect the device isolation regions and the active regions.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the at least four gate electrodes are adjacent to each other.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein the two device gate electrodes are adjacent to each other, and wherein the two device isolation gate electrodes are disposed both sides of the two device gate electrodes.

### Claim 11 (depends on 6)

The semiconductor device of claim 6, wherein the at least four gate electrodes are disposed at higher level than the surface of the semiconductor substrate.

### Claim 12 (depends on 6)

The semiconductor device of claim 6, wherein the two device gate electrodes have extending portions in trenches of the semiconductor substrate.