# US 8,569,847 B2 · Nonvolatile semiconductor memory device

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- Number: US 8,569,847 B2
- Document ID: US8569847B2
- Status: Granted
- Kind: B2
- Application number: 13/236,690
- Filed: 2011-09-20
- Published: 2012-09-27
- Granted: 2013-10-29
- Earliest claimed: 2011-03-24
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Masato Endo
- Inventors: Masato Endo
- Web page: https://patentgrep.com/patent/US8569847B2

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A nonvolatile semiconductor memory device in one embodiment includes a select gate switch transistor having a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second source/drain regions provided in the semiconductor substrate so as to face each other across the gate electrode. The first source/drain region includes a first n-type impurity layer and a second n-type impurity layer which has a higher impurity concentration and has a shallower depth than the first n-type impurity layer. The second source/drain region has a third n-type impurity layer which has a lower impurity concentration and has a shallower depth than the first n-type impurity layer and a fourth n-type impurity layer which has a higher impurity concentration and has a deeper depth than the third n-type impurity layer.

## Claims

### Claim 1

A nonvolatile semiconductor memory device having a select gate switch transistor, a memory cell, and a select gate transistor provided next to the memory cell, the select gate switch transistor comprising:
a gate insulating film formed on a semiconductor substrate;
a gate electrode formed on the gate insulating film; and
a first source/drain region and a second source/drain region formed in the semiconductor substrate so as to face each other,
wherein the first source/drain region includes a first n-type impurity layer and a second n-type impurity layer having a higher impurity concentration and a shallower depth than the first n-type impurity layer,
the second source/drain region includes a third n-type impurity layer having a lower impurity concentration and a shallower depth than the first n-type impurity layer and a fourth n-type impurity layer having a higher impurity concentration and a deeper depth than the third n-type impurity layer,
the second source/drain region is connected to a gate electrode of the select gate transistor via a wiring, and
a closest distance between the gate electrode of the select gate switch transistor and the fourth n-type impurity layer is more than a closest distance between the gate electrode of the select gate switch transistor and the second n-type impurity layer.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the first source/drain region is connected to a gate voltage generation circuit for generating a gate voltage of the select gate transistor.

### Claim 3 (depends on 1)

The device according to claim 1, wherein a distance between the gate electrode of the select gate switch transistor and a device isolation region or a gate electrode of another adjacent select gate switch transistor at a side of the first source/drain region is less than a distance between the gate electrode of the select gate switch transistor and a device isolation region or a gate electrode of still another adjacent select gate switch transistor at a side of the second source/drain region.

### Claim 4 (depends on 1)

The device according to claim 1, wherein an impurity of the second n-type impurity layer is arsenic (As), and an impurity of the fourth n-type impurity layer is phosphorus (P).

### Claim 5 (depends on 1)

The device according to claim 1, wherein impurities of the second n-type impurity layer and the fourth n-type impurity layer are arsenic (As).

### Claim 6 (depends on 5)

The device according to claim 5, wherein the second source/drain region further includes a fifth n-type impurity layer having the same impurity concentration and depth as the first n-type impurity layer, and
the second n-type impurity layer and the fourth n-type impurity layer have the same impurity concentration and depth.

### Claim 7 (depends on 6)

The device according to claim 6, wherein the impurity concentration of the fifth n-type impurity layer is 1E18 atoms/cm3 to 1E20 atoms/cm3.

### Claim 8 (depends on 1)

The device according to claim 1, wherein the first source/drain region of the select gate switch transistor is shared as a source/drain region for another adjacent select gate switch transistor.

### Claim 9 (depends on 1)

The device according to claim 1, wherein the second source/drain region of the select gate switch transistor is shared as a source/drain region for another adjacent select gate switch transistor.

### Claim 10 (depends on 1)

The device according to claim 1, wherein the first source/drain region of the select gate switch transistor is shared as a source/drain region for another adjacent select gate switch transistor, and
the second source/drain region of the select gate switch transistor is shared as a source/drain region for still another adjacent select gate switch transistor.

### Claim 11 (depends on 1)

The device according to claim 1, wherein the impurity concentration of the first n-type impurity layer is 1E18 atoms/cm3 to 1E20 atoms/cm3.

### Claim 12 (depends on 1)

The device according to claim 1, wherein the impurity concentration of the second n-type impurity layer is 1E19 atoms/cm3 to 1E21 atoms/cm3.

### Claim 13 (depends on 1)

The device according to claim 1, wherein the impurity concentration of the third n-type impurity layer is 1E17 atoms/cm3 to 1E19 atoms/cm3.

### Claim 14 (depends on 1)

The device according to claim 1, wherein the impurity concentration of the fourth n-type impurity layer is 1E19 atoms/cm3 to 1E21 atoms/cm3.