Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices

A semiconductor device arrangement, comprising:

• a first semiconductor device having a load path;
• and
• a plurality of second transistors, each having a control terminal and a load path between a first load terminal and a second load terminal;
• wherein the second transistors have their load paths connected in series and connected in series to the load path of the first semiconductor device,
• wherein one of the second transistors has its control terminal connected to a load terminal of the first semiconductor device,
• wherein each but the one of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and
• wherein the second transistors are implemented as FINFETs, each second transistor comprising:
• at least one semiconductor fin;
• a source region, a body region and a drain region arranged in the at least one semiconductor fin, wherein the body region is arranged between the source region and the drain region;
• and
• a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric.

A semiconductor device arrangement, comprising:

• a first semiconductor device having a load path;
• a plurality of second transistors, each having a control terminal and a load path between a first load terminal and a second load terminal;
• at least one voltage limiting element coupled in parallel with at least one second transistor and/or in parallel to the first semiconductor device;
• wherein the second transistors have their load paths connected in series and connected in series to the load path of the first semiconductor device,
• wherein one of the second transistors has its control terminal connected to a load terminal of the first semiconductor device, and
• wherein each but the one of the second transistors has its control terminal connected to the load terminal of one of the other second transistors.

A semiconductor device, comprising:

• a semiconductor substrate;
• a source region disposed in the semiconductor substrate;
• a gate electrode overlying and insulated from the substrate;
• a channel region disposed in the semiconductor substrate beneath the gate electrode and adjacent the source region;
• a drift region disposed in the semiconductor substrate adjacent the channel region;
• a drain region disposed in the semiconductor substrate and laterally spaced from the source region by the channel region and the drift region;
• and
• a plurality of transistor devices formed in the drift region.