# US 8,569,841 B2 · Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,569,841 B2
- Document ID: US8569841B2
- Status: Granted
- Kind: B2
- Application number: 12/754,147
- Filed: 2010-04-05
- Published: 2010-10-07
- Granted: 2013-10-29
- Earliest claimed: 2008-03-13
- Assignees: Tela Innovations, Inc.
- Applicants: Scott T. Becker; Jim Mali; Carole Lambert
- Inventors: Scott T. Becker; Jim Mali; Carole Lambert
- Web page: https://patentgrep.com/patent/US8569841B2

## CPC

- H10D 84/907: {CMOS gate arrays}
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/10: SRAM devices comprising bipolar components
- H10B 10/12: {comprising a MOSFET load element}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 89/10: Integrated device layouts
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- H10D 84/953: {Sub-micron technology}
- H10D 84/975: {Wiring regions or routing}
- H10D 84/987: {Three levels of metal}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are different, such that the first and second PMOS transistor devices have different widths. Widths of the first and second n-type diffusion regions are different, such that the first and second NMOS transistor devices have different widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.

## Claims

### Claim 1

An integrated circuit, comprising:
a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends, and wherein at least one gate level feature layout channel includes a gate level feature that extends into a neighboring gate level feature layout channel without contacting any other gate level feature within the neighboring gate level feature layout channel,
wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type, wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction,
wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the first transistor type,
wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the second transistor type, wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction,
wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
wherein the second gate level feature is electrically connected to the fifth gate level feature, and wherein the third gate level feature is electrically connected to the fourth gate level feature,
wherein the second and third transistors of the first transistor type are positioned between the first and fourth transistors of the first transistor type in the second direction,
wherein the second and third transistors of the second transistor type are positioned between the first and fourth transistors of the second transistor type in the second direction,
wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, and
wherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node.

### Claim 2 (depends on 1)

An integrated circuit as recited in claim 1, wherein each gate level feature within the gate electrode level region is formed to provide electrical conduction along its length extending between the first and second line end spacings adjacent to which its first and second line ends are respectively located.

### Claim 3 (depends on 1)

An integrated circuit as recited in claim 1, further comprising:
a first gate contact defined to physically contact the second gate level feature;
a second gate contact defined to physically contact the third gate level feature;
a third gate contact defined to physically contact the fourth gate level feature; and
a fourth gate contact defined to physically contact the fifth gate level feature,
wherein each of the first, second, third, and fourth gate contacts are respectively positioned over the inner portion of the gate electrode level region.

### Claim 4 (depends on 3)

An integrated circuit as recited in claim 3, wherein the second gate level feature has a first extension distance as measured in the first direction away from the first gate contact and toward the third gate level feature,
wherein the third gate level feature has a second extension distance as measured in the first direction away from the second gate contact and toward the second gate level feature,
wherein the fourth gate level feature has a third extension distance as measured in the first direction away from the third gate contact and toward the fifth gate level feature,
wherein the fifth gate level feature has a fourth extension distance as measured in the first direction away from the fourth gate contact and toward the fourth gate level feature, and
wherein at least two of the first, second, third, and fourth extension distances are different.

### Claim 5 (depends on 4)

An integrated circuit as recited in claim 4, wherein the first gate contact is offset from the third gate contact in the first direction.

### Claim 6 (depends on 5)

An integrated circuit as recited in claim 5, wherein the second and third transistors of the first transistor type share a first diffusion region of a first diffusion type,
wherein the second and third transistors of the second transistor type share a first diffusion region of a second diffusion type, and
wherein the first diffusion region of the first diffusion type is electrically connected to the first diffusion region of the second diffusion type through the common node.

### Claim 7 (depends on 6)

An integrated circuit as recited in claim 6, further comprising:
at least two interconnect levels formed above the gate electrode level region, wherein an electrical connection between the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type is formed in part by two conductive features respectively formed in two interconnect levels, at least one of the two conductive features having a linear-shape.

### Claim 8 (depends on 6)

An integrated circuit as recited in claim 6, further comprising:
at least one interconnect level formed above the gate electrode level region, wherein an electrical connection between the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type extends through only one interconnect level.

### Claim 9 (depends on 3)

An integrated circuit as recited in claim 3, wherein two of the first, second, third, and fourth gate contacts are aligned in the first direction.

### Claim 10 (depends on 9)

An integrated circuit as recited in claim 9, wherein the first and third gate contacts are offset from each other in the first direction.

### Claim 11 (depends on 10)

An integrated circuit as recited in claim 10, wherein the second gate level feature has a first extension distance as measured in the first direction away from the first gate contact and toward the third gate level feature,
wherein the third gate level feature has a second extension distance as measured in the first direction away from the second gate contact and toward the second gate level feature,
wherein the fourth gate level feature has a third extension distance as measured in the first direction away from the third gate contact and toward the fifth gate level feature,
wherein the fifth gate level feature has a fourth extension distance as measured in the first direction away from the fourth gate contact and toward the fourth gate level feature, and
wherein at least two of the first, second, third, and fourth extension distances are different.

### Claim 12 (depends on 11)

An integrated circuit as recited in claim 11, wherein the second and third transistors of the first transistor type share a first diffusion region of a first diffusion type,
wherein the second and third transistors of the second transistor type share a first diffusion region of a second diffusion type, and
wherein the first diffusion region of the first diffusion type is electrically connected to the first diffusion region of the second diffusion type through the common node.

### Claim 13 (depends on 12)

An integrated circuit as recited in claim 12, further comprising:
at least two interconnect levels formed above the gate electrode level region, wherein an electrical connection between the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type is formed in part by two conductive features respectively formed in two interconnect levels, at least one of the two conductive features having a linear-shape.

### Claim 14 (depends on 12)

An integrated circuit as recited in claim 12, further comprising:
at least one interconnect level formed above the gate electrode level region, wherein an electrical connection between the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type extends through only one interconnect level.

### Claim 15 (depends on 3)

An integrated circuit as recited in claim 3, wherein two of the second, third, fourth, and fifth gate level features has a different length as measured in the first direction.

### Claim 16 (depends on 15)

An integrated circuit as recited in claim 15, wherein the second gate level feature has a first extension distance as measured in the first direction away from the first gate contact and toward the third gate level feature,
wherein the third gate level feature has a second extension distance as measured in the first direction away from the second gate contact and toward the second gate level feature,
wherein the fourth gate level feature has a third extension distance as measured in the first direction away from the third gate contact and toward the fifth gate level feature,
wherein the fifth gate level feature has a fourth extension distance as measured in the first direction away from the fourth gate contact and toward the fourth gate level feature, and
wherein at least two of the first, second, third, and fourth extension distances are different.

### Claim 17 (depends on 16)

An integrated circuit as recited in claim 16, wherein the first and third gate contacts are offset from each other in the first direction.

### Claim 18 (depends on 17)

An integrated circuit as recited in claim 17, wherein the second and third transistors of the first transistor type share a first diffusion region of a first diffusion type,
wherein the second and third transistors of the second transistor type share a first diffusion region of a second diffusion type, and
wherein the first diffusion region of the first diffusion type is electrically connected to the first diffusion region of the second diffusion type through the common node.

### Claim 19 (depends on 18)

An integrated circuit as recited in claim 18, further comprising:
at least two interconnect levels formed above the gate electrode level region, wherein an electrical connection between the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type is formed in part by two conductive features respectively formed in two interconnect levels, at least one of the two conductive features having a linear-shape.

### Claim 20 (depends on 18)

An integrated circuit as recited in claim 18, further comprising:
at least one interconnect level formed above the gate electrode level region, wherein an electrical connection between the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type extends through only one interconnect level.

### Claim 21 (depends on 1)

An integrated circuit as recited in claim 1, wherein two of the second, third, fourth, and fifth gate level features has a different length as measured in the first direction.

### Claim 22 (depends on 21)

An integrated circuit as recited in claim 21, wherein the second and fourth gate level features have a substantially equal length as measured in the first direction.

### Claim 23 (depends on 22)

An integrated circuit as recited in claim 22, wherein each transistor within the gate electrode level region is positioned next to and spaced apart from at least one other transistor in accordance with an equal pitch as measured in the second direction.

### Claim 24 (depends on 23)

An integrated circuit as recited in claim 23, wherein the second and third transistors of the first transistor type share a first diffusion region of a first diffusion type,
wherein the second and third transistors of the second transistor type share a first diffusion region of a second diffusion type, and
wherein the first diffusion region of the first diffusion type is electrically connected to the first diffusion region of the second diffusion type through the common node.

### Claim 25 (depends on 24)

An integrated circuit as recited in claim 24, further comprising:
at least two interconnect levels formed above the gate electrode level region, wherein an electrical connection between the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type is formed in part by two conductive features respectively fowled in two interconnect levels, at least one of the two conductive features having a linear-shape.

### Claim 26 (depends on 24)

An integrated circuit as recited in claim 24, further comprising:
at least one interconnect level formed above the gate electrode level region, wherein an electrical connection between the first diffusion region of the first diffusion type and the first diffusion region of the second diffusion type extends through only one interconnect level.

### Claim 27 (depends on 23)

An integrated circuit as recited in claim 23, wherein the gate electrode level region includes a seventh gate level feature that does not form a gate electrode of a transistor, wherein the seventh gate level feature is linear-shaped and is positioned next to and spaced apart from at least one transistor in accordance with the equal pitch as measured in the second direction.

### Claim 28 (depends on 23)

An integrated circuit as recited in claim 23, wherein at least two of the first, second, third, fourth, fifth, and sixth gate level features are linear-shaped.

### Claim 29 (depends on 28)

An integrated circuit as recited in claim 28, wherein the gate electrode level region includes a seventh gate level feature that does not form a gate electrode of a transistor, wherein the seventh gate level feature is linear-shaped and is positioned next to and spaced apart from at least one transistor in accordance with the equal pitch as measured in the second direction.

### Claim 30

A method for creating a layout of an integrated circuit, comprising:
operating a computer to define a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends, and wherein at least one gate level feature layout channel includes a gate level feature that extends into a neighboring gate level feature layout channel without contacting any other gate level feature within the neighboring gate level feature layout channel,
wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type, wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction,
wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the first transistor type,
wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the second transistor type, wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction,
wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
wherein the second gate level feature is electrically connected to the fifth gate level feature, and wherein the third gate level feature is electrically connected to the fourth gate level feature,
wherein the second and third transistors of the first transistor type are positioned between the first and fourth transistors of the first transistor type in the second direction,
wherein the second and third transistors of the second transistor type are positioned between the first and fourth transistors of the second transistor type in the second direction,
wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, and
wherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node.

### Claim 31

A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:
program instructions for defining a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends, and wherein at least one gate level feature layout channel includes a gate level feature that extends into a neighboring gate level feature layout channel without contacting any other gate level feature within the neighboring gate level feature layout channel,
wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type, wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction,
wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the first transistor type,
wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the second transistor type, wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction,
wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
wherein the second gate level feature is electrically connected to the fifth gate level feature, and wherein the third gate level feature is electrically connected to the fourth gate level feature,
wherein the second and third transistors of the first transistor type are positioned between the first and fourth transistors of the first transistor type in the second direction,
wherein the second and third transistors of the second transistor type are positioned between the first and fourth transistors of the second transistor type in the second direction,
wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, and
wherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node.