# US 8,569,837 B2 · MOS devices having elevated source/drain regions

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- Number: US 8,569,837 B2
- Document ID: US8569837B2
- Status: Granted
- Kind: B2
- Application number: 11/800,615
- Filed: 2007-05-07
- Published: 2008-11-13
- Granted: 2013-10-29
- Earliest claimed: 2007-05-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Chih-Hsin Ko; Hung-Wei Chen; Chung-Hu Ke; Ta-Ming Kuan; Wen-Chin Lee
- Inventors: Chih-Hsin Ko; Hung-Wei Chen; Chung-Hu Ke; Ta-Ming Kuan; Wen-Chin Lee
- Web page: https://patentgrep.com/patent/US8569837B2

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.

## Claims

### Claim 1

A semiconductor structure comprising:
a semiconductor substrate;
a gate dielectric over the semiconductor substrate;
a gate electrode over the gate dielectric;
a deep source/drain region adjacent the gate electrode;
a silicide region directly on a surface of the deep source/drain region;
an elevated metallized source/drain region between the silicide region and the gate electrode, wherein the elevated metallized source/drain region adjoins the silicide region, wherein the silicide region has a different composition than the elevated metallized source/drain region; and
a lightly doped source/drain (LDD) region underlying the elevated metallized source/drain region.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the elevated metallized source/drain region comprises same metals as the silicide region.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the elevated metallized source/drain region has a Schottky contact with the LDD region.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the LDD region comprises epitaxy silicon.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the elevated metallized source/drain region is spaced apart from the gate dielectric and the gate electrode by a spacer, and wherein the spacer has a thickness of less than about 150 Å.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the deep source/drain region comprises a stressor having an inner edge substantially vertically aligned to an interface between the silicide region and the elevated metallized source/drain region.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the stressor comprises silicon germanium (SiGe).

### Claim 8 (depends on 6)

The semiconductor structure of claim 6, wherein the stressor comprises carbon-doped silicon (SiC).

### Claim 9 (depends on 6)

The semiconductor structure of claim 6, wherein the silicide region has a bottom surface higher than a bottom surface of the gate dielectric.

### Claim 10

A semiconductor structure comprising:
a semiconductor substrate;
a gate dielectric over the semiconductor substrate;
a gate electrode over the gate dielectric;
a stressor in the semiconductor substrate and adjacent the gate electrode, an upper surface of the stressor being silicided;
an elevated metallized source/drain region between the upper surface of the stressor and the gate electrode, wherein the elevated metallized source/drain region has a bottom surface substantially higher than a top surface of the semiconductor substrate, the elevated metallized source/drain region and the upper surface of the stressor comprising different materials; and
a lightly doped source/drain (LDD) region underlying the elevated metallized source/drain region.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the elevated metallized source/drain region is continuously connected to a silicide region over the stressor.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the silicide region comprises a material selected from the group consisting essentially of germanium and carbon, and wherein the elevated metallized source/drain region is substantially free from the material.

### Claim 13 (depends on 10)

The semiconductor structure of claim 10 further comprising an epitaxy silicon layer between the semiconductor substrate and the elevated metallized source/drain region.

### Claim 14 (depends on 10)

The semiconductor structure of claim 10 further comprising a spacer on sidewalls of the gate dielectric and the gate electrode, wherein the spacer horizontally adjoins the gate electrode and the elevated metallized source/drain region, and wherein the spacer has a thickness of less than about 150 Å.

### Claim 15

A semiconductor structure comprising:
a semiconductor substrate comprising an NMOS region and a PMOS region;
an NMOS device in the NMOS region, the NMOS device comprising:
a first gate stack on the semiconductor substrate;
a first spacer on a sidewall of the first gate stack;
a first deep source/drain region adjacent the first gate stack;
a first silicide region directly on a surface of the first deep source/drain region;
a first elevated metallized source/drain region between the first silicide region and the first gate stack; and
a first lightly doped source/drain (LDD) region underlying the first elevated metallized source/drain region; and
a PMOS device in the PMOS region, the PMOS device comprising:
a second gate stack on the semiconductor substrate;
a second spacer on a sidewall of the second gate stack;
a second deep source/drain region adjacent the second gate stack;
a second silicide region directly on a surface of the second deep source/drain region;
a second elevated metallized source/drain region between the second silicide region and the second gate stack, the second elevated metallized source/drain region comprising at least one different element than the second silicide; and
a second lightly doped source/drain (LDD) region underlying the second elevated metallized source/drain region.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the first and the second elevated metallized source/drain regions are silicide regions comprising same metals.

### Claim 17 (depends on 15)

The semiconductor structure of claim 15, wherein the first deep source/drain region comprises carbon-doped silicon (SiC), and the second deep source/drain region comprises silicon germanium (SiGe).

### Claim 18 (depends on 15)

The semiconductor structure of claim 15, wherein each of the first and the second spacers has a thickness of less than about 150 Å.