# US 8,569,834 B2 · Accumulation field effect microelectronic device and process for the formation thereof

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- Number: US 8,569,834 B2
- Document ID: US8569834B2
- Status: Granted
- Kind: B2
- Application number: 12/102,398
- Filed: 2008-04-14
- Published: 2008-10-16
- Granted: 2013-10-29
- Earliest claimed: 2007-04-12
- Assignees: The Penn State Research Foundation
- Applicants: Stephen J. Fonash; Yinghui Shan; Somasundaram Ashok
- Inventors: Stephen J. Fonash; Yinghui Shan; Somasundaram Ashok
- Web page: https://patentgrep.com/patent/US8569834B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/121: {oriented parallel to substrates}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance.

## Claims

### Claim 1

A gated microelectronic device comprising:
an insulator substrate;
a source
supported on said insulator substrate, said source with a source ohmic contact;
said source
having
a source dopant type and
a source dopant concentration and defining
a source linear extent and
a source thickness;
a drain
supported on said insulator substrate, said drain with a drain ohmic contact;
said drain
having a
drain dopant type and
drain dopant concentration and defining
a drain linear extent and
a drain thickness;
a channel portion intermediate between said source and said drain,
said channel portion
supported on said insulator substrate and having a
channel portion dopant type and
channel portion dopant concentration and defining
a channel portion linear extent and
a channel portion thickness,
said channel portion being a thin film
an insulative dielectric in contact with said channel portion;
a gate in overlying contact with said insulative dielectric, said gate defining a gate-insulative dielectric interface;
said channel portion having a dimension normal to the gate-insulative dielectric interface suitable to fully deplete in an off-state;
a gate contact applying a gate voltage bias to control charge carrier accumulation and depletion in said channel portion; and
the source dopant, the drain dopant, and the channel portion dopant being all of a same type and
wherein the source dopant concentration the channel dopant concentration, and the drain concentration are equivalent;
wherein the source dopant concentration is between 1012 per cm3 and 1019 per cm3; and
wherein the source linear extent, the drain linear extent, and the positioning of the source ohmic contact and drain ohmic contact prevent ambipolar behavior in the device.

### Claim 2 (depends on 1)

The device of claim 1 wherein the doping type is p-type and the gate voltage bias is negative and the drain voltage bias is negative with respect to said source to yield a device on-state status.

### Claim 3 (depends on 1)

The device of claim 1 wherein the doping type is p-type and the gate voltage bias is positive and the drain voltage bias is negative with respect to said source to yield a device off-state status.

### Claim 4 (depends on 1)

The device of claim 1 wherein the source linear extent and the drain linear extent create a minority carrier density in said source and said drain proximal to channel edges that is substantially equivalent under the gate voltage bias to that present in the absence of any applied voltages.

### Claim 5 (depends on 1)

The device of claim 1 wherein the dimension of said channel region normal to the gate-insulative dielectric interface is between 5 and 100 nanometers.

### Claim 6 (depends on 1)

The device of claim 1 wherein said channel portion is an ultra thin semiconductor or a semiconductor ribbon having a thickness of between 5 and 100 nanometers.

### Claim 7 (depends on 1)

The device of claim 1 wherein said channel portion is formed from a semiconductor selected from the group comprising: organic semiconductors, silicon, germanium, II-VI semiconductors, III-V semiconductors, and carbon materials.

### Claim 8 (depends on 1)

The device of claim 1 wherein said device is used for controlling currents or voltages in display applications.

### Claim 9 (depends on 1)

The device of claim 1 wherein said device is used in electrostatic protection.

### Claim 10 (depends on 1)

The device of claim 1 wherein said device is used in sensor applications.

### Claim 11 (depends on 1)

The device of claim 1 wherein said device is used in circuit element applications.

### Claim 12 (depends on 1)

The device of claim 1 further comprising a second gate intermediate between said source and said drain.

### Claim 13 (depends on 1)

The device of claim 1 wherein the doping type is n-type, said channel is ultra-thin and the gate voltage bias is positive and the drain voltage bias is positive with respect to said source to yield a device on-state status.

### Claim 14 (depends on 1)

The device of claim 1 wherein the doping type is n-type, said channel is ultra-thin and the gate voltage bias is positive and the drain voltage bias is positive with respect to said source to yield a device off-state status.

### Claim 15

A gated microelectronic device comprising:
a source
with a source ohmic contact;
said source
having
a source dopant type and
a source dopant concentration and defining
a source linear extent and
a source thickness;
a drain
with a drain ohmic contact;
said drain
having a
drain dopant type and
drain dopant concentration and defining
a drain linear extent and
a drain thickness;
a channel portion intermediate between said source and said drain,
said channel portion
having a
channel portion dopant type and
channel portion dopant concentration and defining
a channel portion linear extent and
a channel portion thickness,
said channel portion being a thin film
an insulative dielectric in contact with said channel portion;
a gate in overlying contact with said insulative dielectric, said gate defining a gate-insulative dielectric interface;
said channel portion having a dimension normal to the gate-insulative dielectric interface suitable to fully deplete in an off-state;
a gate contact applying a gate voltage bias to control charge carrier accumulation and depletion in said channel portion; and
the source dopant, the drain dopant, and the channel portion dopant being all of a same type; and
wherein the source dopant concentration the channel dopant concentration, and the drain concentration are equivalent;
wherein the source linear extent, the drain linear extent, and the positioning of the source ohmic contact and drain ohmic contact prevent ambipolar behavior in the device.

### Claim 16 (depends on 15)

The device of claim 15 wherein the source dopant concentration is between 1012 per cm3 and 1019 per cm3.

### Claim 17

A gated microelectronic device comprising:
an insulator substrate;
a source
supported on said insulator substrate, said source with a source ohmic contact;
said source
having
a source dopant type and
a source dopant concentration and defining
a source linear extent and
a source thickness;
a drain
supported on said insulator substrate, said drain with a drain ohmic contact;
said drain
having a
drain dopant type and
drain dopant concentration and defining
a drain linear extent and
a drain thickness;
a channel portion intermediate between said source and said drain,
said channel portion
supported on said insulator substrate and
having a
channel portion dopant type and
channel portion dopant concentration and defining
a channel portion linear extent and
a channel portion thickness,
said channel portion being a thin film,
said channel region normal to the gate-insulative dielectric interface having a dimension of between 5 and 100 nanometers;
an insulative dielectric in contact with said channel portion;
a gate in overlying contact with said insulative dielectric, said gate defining a gate-insulative dielectric interface;
said channel portion having a dimension normal to the gate-insulative dielectric interface suitable to fully deplete in an off-state;
a gate contact applying a gate voltage bias to control charge carrier accumulation and depletion in said channel portion; and
the source dopant, the drain dopant, and the channel portion dopant being all of a same type and
wherein the source dopant concentration the channel dopant concentration, and the drain concentration are equivalent;
wherein the source linear extent, the drain linear extent, and the positioning of the source ohmic contact and drain ohmic contact prevent ambipolar behavior in the device.

### Claim 18 (depends on 17)

The device of claim 17 wherein the source dopant concentration is between 1012 per cm3 and 1019 per cm3.

### Claim 19 (depends on 17)

The device of claim 17 wherein the source linear extent and the drain linear extent create a minority earner density in said source and said drain proximal to channel edges that is substantially equivalent under the gate voltage bias to that present in the absence of any applied voltages.

### Claim 20 (depends on 17)

The device of claim 17 wherein said channel portion is formed from a semiconductor selected from the group comprising: organic semiconductors, silicon, germanium, II-VI semiconductors, III-V semiconductors, and carbon materials.

### Claim 21 (depends on 17)

The device of claim 17 wherein said device is used for controlling currents or voltages in display applications.

### Claim 22 (depends on 17)

The device of claim 17 wherein said device is used in electrostatic protection.

### Claim 23 (depends on 17)

The device of claim 17 wherein said device is used in sensor applications.

### Claim 24 (depends on 17)

The device of claim 17 wherein said device is used in circuit element applications.

### Claim 25 (depends on 17)

The device of claim 17 further comprising a second gate intermediate between said source and said drain.