# US 8,569,833 B2 · LDMOS device structure and manufacturing method of the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,569,833 B2
- Document ID: US8569833B2
- Status: Granted
- Kind: B2
- Application number: 13/271,120
- Filed: 2011-10-11
- Published: 2012-04-19
- Granted: 2013-10-29
- Earliest claimed: 2010-10-13
- Assignees: Shanghai Hua Hong NEC Electronics Co., Ltd.
- Applicants: Shuai Zhang; Haijun Wang
- Inventors: Shuai Zhang; Haijun Wang
- Web page: https://patentgrep.com/patent/US8569833B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention discloses an LDMOS device structure, including a MOS transistor cell, wherein an isolation region is formed on each outer side of both a source region and a drain region of the MOS transistor cell; each isolation region includes a plurality of isolation trenches and isolates the MOS transistor cell from its surroundings; the height of the isolation region is smaller than that of a gate of the MOS transistor cell. The present invention also discloses a manufacturing method of the LDMOS device structure, including forming isolation trenches by lithography and etching processes, then forming isolation regions of SiO2 by depleting silicon between isolation trenches through high-temperature drive-in. The present invention can reduce parasitic capacitance, surface unevenness and difficulty of subsequent process and realize the production of small-size gate devices by forming a thicker field oxide layer and a gap structure of isolation trenches.

## Claims

### Claim 1

An LDMOS device structure, comprising a MOS transistor cell, wherein an isolation region is formed on each outer side of both a source region and a drain region of the MOS transistor cell;
each isolation region formed of silicon dioxide comprises a plurality of isolation trenches and isolates the MOS transistor cell from its surroundings;
a height of the isolation region is shorter than or equal to that of a gate of the MOS transistor cell,
wherein air gaps exist in the isolation trenches.

### Claim 2 (depends on 1)

The LDMOS device structure according to claim 1, wherein the isolation trenches are deep trenches.

### Claim 3 (depends on 1)

The LDMOS device defined by claim 1 further comprising:
(i) an isolation layer formed on a substrate,
(ii) a connecting layer formed on and connected to said substrate and said source in the isolation layer.

### Claim 4 (depends on 3)

The LDMOS device defined by claim 3, wherein the isolation trenches are deep trenches.