# US 8,569,832 B2 · Vertical transistor having first and second tensile layers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,832 B2 - Document ID: US8569832B2 - Status: Granted - Kind: B2 - Application number: 13/314,532 - Filed: 2011-12-08 - Published: 2012-04-05 - Granted: 2013-10-29 - Earliest claimed: 2008-01-02 - Assignees: Hynix Semiconductor Inc. - Applicants: Eun Sung Lee - Inventors: Eun Sung Lee - Web page: https://patentgrep.com/patent/US8569832B2 ## CPC - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe - H10D 62/8325: {Silicon carbide} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern. ## Claims ### Claim 1 A vertical transistor, comprising: a semiconductor substrate having a pillar-shaped active pattern over a surface thereof; a first tensile layer formed over the semiconductor substrate at a lower end portion of the pillar-shaped active pattern and a second tensile layer formed at an upper end portion of the pillar-shaped active pattern, the first and second tensile layers applying a tensile stress to the pillar-shaped active pattern in a vertical direction; a first junction region formed within the surface of the semiconductor substrate below the first tensile layer and the pillar-shaped active pattern; a gate surrounding at least a portion of the pillar-shaped active pattern; and a second junction region formed within the upper end portion of the pillar-shaped active pattern wherein the first tensile layer is formed only over the semiconductor substrate at a lower end portion of the pillar-shaped active pattern and the second tensile layer is formed only at an upper end portion of the pillar-shaped active pattern, the first and second tensile layers applying a tensile stress to a channel region of the pillar-shaped active pattern in a vertical direction. ### Claim 2 (depends on 1) The vertical transistor according to claim 1, wherein the pillar-shaped active pattern comprises an epitaxial Si layer. ### Claim 3 (depends on 1) The vertical transistor according to claim 1, wherein the first and second tensile layers each comprises a Si1-xCx layer. ### Claim 4 (depends on 3) The vertical transistor according to claim 3, wherein x is in a range of 0.01≦x≦0.05. ### Claim 5 (depends on 1) The vertical transistor according to claim 1, wherein the second tensile layer is formed so as to cover side and upper surfaces of the upper end portion of the pillar-shaped active pattern. ### Claim 6 (depends on 1) The vertical transistor according to claim 1, wherein the first tensile layer is formed so as to surround the lower end portion of the pillar-shaped active pattern. ### Claim 7 A vertical transistor, comprising: a semiconductor substrate having a pillar-shaped active pattern over a surface thereof; a first tensile layer comprising a Si1-xCx layer formed over the semiconductor substrate at a lower end portion of the pillar-shaped active pattern; a second tensile layer comprising a Si1-xCx layer formed at an upper end portion of the pillar-shaped-active pattern; a first junction region formed within the surface of the semiconductor substrate below the first tensile layer and the pillar-shaped active pattern; a gate surrounding at least a portion of the pillar-shaped active pattern; and a second junction region formed within the upper end portion of the pillar-shaped active pattern, wherein the first tensile layer is formed only over the semiconductor substrate at a lower end portion of the pillar-shaped active pattern and the second tensile layer is formed only at an upper end portion of the pillar-shaped active pattern, the first and second tensile layers applying a tensile stress to a channel region of the pillar-shaped active pattern in a vertical direction. ### Claim 8 (depends on 7) The vertical transistor according to claim 7, wherein the pillar-shaped active pattern comprises an epitaxial Si layer. ### Claim 9 (depends on 8) The vertical transistor according to claim 8, wherein the gate comprises an Si layer and an insulation layer surrounding the eptiaxial Si layer. ### Claim 10 (depends on 7) The vertical transistor according to claim 7, wherein x is in a range of 0.01≦x≦0.05. ### Claim 11 (depends on 7) The vertical transistor according to claim 7, wherein the second tensile layer is formed so as to cover side and upper surfaces of the upper end portion of the pillar-shaped active pattern. ### Claim 12 (depends on 7) The vertical transistor according to claim 7, wherein the first tensile layer is formed so as to surround the lower end portion of the pillar-shaped active pattern. ### Claim 13 (depends on 7) The vertical transistor according to claim 7, wherein the second junction region comprises N-type impurities, and first and second insulation layers are formed over the second tensile layer so as to cover the second tensile layer, the first and second insulation layers having a hole therein exposing a portion of the second tensile layer at the upper surface of the pillar-shaped active pattern.