# US 8,569,831 B2 · Integrated circuit arrays and semiconductor constructions

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- Number: US 8,569,831 B2
- Document ID: US8569831B2
- Status: Granted
- Kind: B2
- Application number: 13/117,408
- Filed: 2011-05-27
- Published: 2012-11-29
- Granted: 2013-10-29
- Earliest claimed: 2011-05-27
- Assignees: Micron Technology, Inc.
- Applicants: Lars P. Heineck; Shyam Surthi; Jaydip Guha
- Inventors: Lars P. Heineck; Shyam Surthi; Jaydip Guha
- Web page: https://patentgrep.com/patent/US8569831B2

## CPC

- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/477: {Vertical HEMTs or vertical HHMTs}
- H10D 30/711: {having floating bodies}
- H10B 12/488: {Word lines}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 64/01328: {by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

## Claims

### Claim 1

An integrated circuit array having rows and columns, comprising:
digit lines under vertically-oriented transistors; the digit lines interconnecting the transistors along columns of the array and being entirely composed of one or more metal-containing materials; the vertically-oriented transistors having bottom source/drain regions electrically coupled to the digit lines;
wherein the digit lines are over a semiconductor deck comprising semiconductor material;
wherein electrically insulative regions are directly between the digit lines and the semiconductor material of the deck; and
wherein the electrically insulative regions include gas-filled cavities.

### Claim 2

An integrated circuit array having rows and columns, comprising:
digit lines under vertically-oriented transistors; the digit lines interconnecting the transistors along columns of the array and being entirely composed of one or more metal-containing materials; the vertically-oriented transistors having bottom source/drain regions electrically coupled to the digit lines;
wherein the digit lines are over a semiconductor deck comprising semiconductor material;
wherein electrically insulative regions are directly between the digit lines and the semiconductor material of the deck; and
further comprising metal-containing material directly between the electrically insulative regions and the semiconductor material of the deck.

### Claim 3

A semiconductor construction, comprising:
an array of vertically-oriented transistors; individual of the transistors comprising a bottom source/drain region, a top source/drain region, and a channel region between the to and bottom source/drain regions; the array comprising rows and columns;
access lines extending along rows of the array to interconnect transistors along said rows, the access lines extending across the channel regions and forming gates across the transistors to gatedly couple the to and bottom source/drain regions through the channel regions;
digit lines extending along columns of the array to interconnect transistors along said columns, the digit lines being electrically coupled to the bottom source/drain regions of the transistors and being comprised entirely of one or more metal-containing materials;
each transistor of the array being uniquely addressed by a combination of an access line and a digit line; and
wherein the semiconductor deck contains semiconductor material directly under the digit lines; the semiconductor construction further comprising electrically insulative regions between the digit lines and the semiconductor material of the deck that is directly under the digit lines.

### Claim 4 (depends on 3)

The semiconductor construction of claim 3 further comprising metal/semiconductor material directly against the bottom source/drain regions; and wherein the digit lines comprise a metal-containing composition directly against the metal/semiconductor material.

### Claim 5 (depends on 4)

The semiconductor construction of claim 4 wherein the metal/semiconductor material is metal silicide.

### Claim 6 (depends on 4)

The semiconductor construction of claim 4 wherein the metal/semiconductor material is configured as lines that are part of the digit lines.

### Claim 7 (depends on 4)

The semiconductor construction of claim 4 wherein the metal/semiconductor material is configured as separated blocks associated with the individual transistors.

### Claim 8 (depends on 4)

The semiconductor construction of claim 4 wherein the metal-containing composition comprises metal nitride, elemental metal, or mixtures of two or more metals.

### Claim 9 (depends on 3)

The semiconductor construction of claim 3 wherein the electrically insulative regions include gas-filled cavities.

### Claim 10 (depends on 3)

The semiconductor construction of claim 3 wherein the electrically insulative regions are entirely electrically insulative material which is at least semisolid.