# US 8,569,830 B2 · Semiconductor device having vertical MOS transistor and method for manufacturing the semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,830 B2 - Document ID: US8569830B2 - Status: Granted - Kind: B2 - Application number: 12/230,562 - Filed: 2008-09-02 - Published: 2009-03-12 - Granted: 2013-10-29 - Earliest claimed: 2007-09-07 - Assignees: Elpida Memory, Inc. - Applicants: Kiyonori Oyu; Yoshihiro Takaishi; Yu Kosuge - Inventors: Kiyonori Oyu; Yoshihiro Takaishi; Yu Kosuge - Web page: https://patentgrep.com/patent/US8569830B2 ## CPC - H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)} - H10B 12/34: {the transistor being at least partially in a trench in the substrate} - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 84/016: {the components including vertical IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10B 12/05: {Making the transistor} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a gate insulating film and a gate electrode to be made a channel part, and diffusion layers to be a source and a drain are included on a top and a bottom of the channel part, electrode which controls potential of a gate electrode material is formed in gate electrode material formed on a side surface of isolation film, in order to eliminate a parasitic MOS operation by the gate electrode material remaining on the side surface of the isolation film. ## Claims ### Claim 1 A semiconductor device including a vertical MOS (metal-oxide semiconductor) transistor, the semiconductor device comprising: an isolation layer formed in a semiconductor substrate configured to define an isolation area and an active area surrounded by said isolation area; a semiconductor pillar formed on said active area; a first gate electrode formed above a sidewall of said semiconductor pillar; a conductive layer formed above a sidewall of said isolation layer; and an electrode electrically coupled to said conductive layer supplying a voltage to prevent said conductive layer from a floating state, wherein the first gate electrode and the conductive layer have the respective sidewall structure including a rounded top surface. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein said first gate electrode is electrically separated from said conductive layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein said first gate electrode is electrically connected to said conductive layer. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, further comprising a bottom diffusion layer formed at the bottom of said pillar, and a top diffusion layer formed at the top of said pillar. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein a bottom of said isolation layer is deeper in a depth direction than that of said bottom diffusion layer. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein said isolation layer comprises a shallow trench isolation layer. ### Claim 7 A semiconductor device including a vertical MOS (metal-oxide semiconductor) transistor, the vertical MOS transistor comprising: a semiconductor pillar formed in an area subjected to a shallow trench isolation layer of a semiconductor substrate, a lower diffusion layer formed shallower than a depth of a shallow trench isolation, in the semiconductor substrate at a lower portion of the semiconductor pillar, an upper diffusion layer formed at an upper portion of the semiconductor pillar, a channel part formed in a region sandwiched by the upper and lower diffusion layers, a gate insulating film and a gate electrode included on a side surface of the channel part; a conductive sidewall formed on a side surface of an insulating film of said shallow trench isolation; and an electrode electrically coupled to said conductive sidewall supplying a voltage to prevent said conductive sidewall from a floating state, wherein said electrode contacts the conductive sidewall via a gate electrode of a dummy transistor, the gate electrode of the dummy transistor comprising the conductive sidewall. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, further comprising the dummy transistor formed between said shallow trench isolation layer and said vertical MOS transistor, and a gate potential of the vertical MOS transistor is controlled through the electrode contacting said conductive sidewall via a gate electrode material of the dummy transistor, the gate electrode material of the dummy transistor including the conductive sidewall. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein a dummy transistor includes a gate electrode material of the conductive layer formed on a side surface of the isolation layer. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein a gate potential of the vertical MOS transistor is controlled by the electrode which contacts the conductive layer via a gate electrode material of a dummy transistor to eliminate the floating state, the conductive layer including the gate electrode material of the dummy transistor. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the electrode is configured to control the potential of a gate electrode material of the conductive layer by the conductive layer being in contact with the first gate electrode through a dummy transistor to prevent the floating state, the conductive layer including the gate electrode material of the dummy transistor. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein a gate potential of the vertical MOS transistor is controlled through the electrode contacting the conductive layer via a gate electrode material of the dummy transistor to be devoid of the conductive layer being in the floating state, the conductive layer including the gate electrode material of the dummy transistor. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, further comprising a dummy transistor formed between the isolation layer and the vertical MOS transistor, and a gate potential of the vertical MOS transistor is controlled through the electrode contacting the conductive layer via a gate electrode material of a dummy transistor, the conductive layer including the gate electrode material of the dummy transistor. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the electrode is configured to control a potential of the conductive layer in order to control a gate potential at the first gate electrode of the vertical MOS transistor. ### Claim 15 (depends on 1) The semiconductor device as claimed in claim 1, wherein the conductive layer includes a first portion being in direct contact with the first gate electrode and a second portion not being in contact with the first gate electrode; and wherein the electrode is arranged at a position where the electrode is in direct touch with the second portion and is not in touch with the first portion. ### Claim 16 (depends on 7) The semiconductor device as claimed in claim 7, wherein the conductive sidewall includes a first portion being in direct contact with the gate electrode and a second portion not being in contact with the gate electrode; and wherein the electrode is arranged at a position where the electrode is in direct touch with the second portion and is not in touch with the first portion. ### Claim 17 (depends on 7) The semiconductor device as claimed in claim 7, wherein the gate electrode and the conductive sidewall have the respective sidewall structure including a rounded top surface. ### Claim 18 (depends on 7) The semiconductor device according to claim 7, wherein the electrode that is electrically coupled to said conductive sidewall is configured to control a supply of the voltage to prevent the conductive sidewall from a floating state. ### Claim 19 A semiconductor device including a vertical MOS (metal-oxide semiconductor) transistor, the semiconductor device comprising: an isolation layer formed in a semiconductor substrate to define an active area; a semiconductor pillar formed on said active area; a gate electrode formed above a sidewall of said semiconductor pillar to wholly surround said semiconductor pillar; a conductive layer formed above a sidewall of said isolation layer; and an electrode formed to be electrically coupled to said conductive layer. ### Claim 20 (depends on 1) The semiconductor device as claimed in claim 1, wherein the conductive layer includes a first portion being in direct contact with the gate electrode and a second portion not being in contact with the gate electrode, and wherein the electrode is arranged at a position where the electrode is in direct contact with the second portion and is not in contact with the first portion. ### Claim 21 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: a dummy transistor formed on a side surface of a shallow trench isolation to be arranged between said isolation layer and said gate electrode, a gate electrode of the dummy transistor comprising the conductive layer, wherein a gate potential of the vertical MOS transistor is controlled through the electrode via the gate electrode of the dummy transistor.