# US 8,569,818 B2 · Blocking layers for leakage current reduction in DRAM devices

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- Number: US 8,569,818 B2
- Document ID: US8569818B2
- Status: Granted
- Kind: B2
- Application number: 13/658,065
- Filed: 2012-10-23
- Published: 2013-05-09
- Granted: 2013-10-29
- Earliest claimed: 2011-11-07
- Assignees: Intermolecular, Inc.
- Applicants: Intermolecular, Inc.
- Inventors: Sandra G. Malhotra; Hanhong Chen; Wim Y. Deweerd; Hiroyuki Ode
- Web page: https://patentgrep.com/patent/US8569818B2

## CPC

- H10D 1/692: {Electrodes}
- H10D 1/68: Capacitors having no potential barriers
- H10B 12/033: {the capacitor extending over the transistor}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

## Claims

### Claim 1

A semiconductor layer stack comprising:
a first electrode layer formed on a substrate;
a dielectric material formed on the first electrode layer,
wherein the dielectric material comprises a dopant;
a blocking layer formed on the dielectric material,
wherein the blocking layer comprises one of Er2O3, Ga2O3, or Gd2O3, has the k value being between about 10 and about 45, and the band gap being greater than about 4.8 eV; and
a second electrode layer formed on the blocking layer.

### Claim 2 (depends on 1)

The semiconductor layer stack of claim 1, wherein the first electrode layer comprises one of a metal, a metal alloy, a conductive metal oxide, a conductive metal silicide, a conductive metal carbide, a conductive metal nitride, or combinations thereof.

### Claim 3 (depends on 2)

The semiconductor layer stack of claim 2 wherein the first electrode layer is a conductive metal oxide comprising one of molybdenum oxide, tungsten oxide, ruthenium oxide, iron oxide, iridium oxide, chromium oxide, manganese oxide, tin oxide, cobalt oxide, or nickel oxide.

### Claim 4 (depends on 3)

The semiconductor layer stack of claim 3 wherein the conductive metal oxide comprises molybdenum oxide.

### Claim 5 (depends on 1)

The semiconductor layer stack of claim 1 wherein the dielectric material comprises one of Al2O3, BaSrTiOX (BST), HfO2, HfSiOX, Nb2O5, PbZrTiOX (PZT), SiO2, a bilayer of SiO2 and SiXNY, SiON, SrTiO3 (STO), Ta2O5, TiO2, ZrO2, or doped versions of the same.

### Claim 6 (depends on 5)

The semiconductor layer stack of claim 5 wherein the dielectric material comprises TiO2, and wherein the dopant comprises one of Al, Ce, Co, Er, Ga, Gd, Ge, Hf, In, La, Lu, Mg, Mn, Nd, Pr, Sc, Si, Sn, Sr, Y, Zr, or combinations thereof.

### Claim 7 (depends on 1)

The semiconductor layer stack of claim 1 wherein the blocking layer is doped.

### Claim 8 (depends on 1)

The semiconductor layer stack of claim 1 wherein the blocking layer is thinner than the dielectric material.

### Claim 9 (depends on 1)

The semiconductor layer stack of claim 1 wherein the thickness of the blocking layer is less than about 2.0 nm.

### Claim 10 (depends on 1)

The semiconductor layer stack of claim 1 wherein the thickness of the blocking layer is between about 0.7 nm and about 1.5 nm.

### Claim 11 (depends on 1)

The semiconductor layer stack of claim 1 wherein the thickness of the blocking layer is less or equal to about 25% of the total dielectric thickness of the capacitor stack.

### Claim 12 (depends on 1)

The semiconductor layer stack of claim 1 wherein the second electrode layer comprises one of Co, CoN, Ir, MoN, MoO2, Ni, NiN, NiO, Pt, Pd, Ru, RuO2, TiN, VN, WN, or combinations thereof.

### Claim 13 (depends on 1)

The semiconductor layer stack of claim 1 wherein the first electrode layer is subjected to an annealing treatment before the formation of the dielectric material.

### Claim 14 (depends on 1)

The semiconductor layer stack of claim 1 wherein the first electrode layer, the dielectric material, and the blocking are subjected to an annealing treatment after the formation of the blocking and before the formation of the second electrode layer.

### Claim 15 (depends on 1)

The semiconductor layer stack of claim 1 wherein the first electrode layer, the dielectric material, the blocking layer, and the second electrode layer are subjected to an annealing treatment after the formation of the second electrode layer.

### Claim 16 (depends on 1)

The semiconductor layer stack of claim 1 wherein a barrier height between the blocking layer and the second electrode layer is greater than about 1.2 eV.

### Claim 17 (depends on 1)

The semiconductor layer stack of claim 1 wherein the blocking layer comprises Er2O3.

### Claim 18 (depends on 17)

The semiconductor layer stack of claim 17 wherein the blocking layer further comprises a dopant, wherein the first electrode comprises MoO2, wherein the dielectric materials comprises TiO2, wherein the dopant of the dielectric materials comprises Al, and wherein the second electrode comprises platinum.

### Claim 19 (depends on 1)

The semiconductor layer stack of claim 1 wherein the blocking layer comprises Ga2O3.

### Claim 20 (depends on 1)

The semiconductor layer stack of claim 1 wherein the blocking layer comprises Gd2O3.