# US 8,569,817 B2 · Semiconductor device and method for fabricating the same

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- Number: US 8,569,817 B2
- Document ID: US8569817B2
- Status: Granted
- Kind: B2
- Application number: 12/839,308
- Filed: 2010-07-19
- Published: 2012-01-19
- Granted: 2013-10-29
- Earliest claimed: 2010-07-15
- Assignees: Hynix Semiconductor Inc.
- Applicants: Se In Kwon
- Inventors: Se In Kwon
- Web page: https://patentgrep.com/patent/US8569817B2

## CPC

- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10B 12/0385: {Making a connection between the transistor and the capacitor, e.g. buried strap}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/48: {Data lines or contacts therefor}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate including an active region defined by a device isolation film;
a bit line hole disposed over the semiconductor substrate;
a spacer disposed at sidewalls of the bit line hole, the bit line spacer including oxide and being free of nitride;
a bit line conductive layer formed in the bit line hole including the oxide film;
a storage node contact hole formed to be adjacent to the bit line hole and exposing the semiconductor substrate; and
a storage node contact plug formed in the storage node contact hole,
wherein the storage node contact plug is formed with at least two conductive materials having different dopant concentration levels,
wherein the storage node contact plug includes:
a lightly doped contact plug disposed in a lower portion of the storage node contact hole; and
a highly doped contact plug disposed in an upper portion of the storage node contact hole and over the lightly doped contact plug.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the spacer is disposed at sidewalls of the storage node contact plug, the spacer contacting the storage node contact plug and the bit line conductive layer, and
wherein a thickness of the spacer formed proximate the lightly doped contact plug is thicker than that of the spacer formed proximate the highly doped contact plug.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the storage node contact hole is obtained from a line pattern that extends along a direction parallel to a gate pattern.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising a first landing plug including polysilicon and disposed over the semiconductor substrate and
electrically coupled to the bit line conductive layer, and
wherein the spacer consists essentially of an oxide film.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising a bit line hard mask disposed over the bit line conductive layer in the bit line hole.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the bit line conductive layer includes:
a barrier metal layer formed over the inner surface of the bit line hole; and
a conductive layer formed over the barrier metal layer to be buried in the bit line hole.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, further comprising a buried gate buried by a given depth in the active region and the device isolation film of the semiconductor substrate.

### Claim 8

A semiconductor device comprising:
a first and a second active regions formed in a substrate, the first and the second active regions being electrically separate by a device isolation region;
a storage node contact plug formed in the first active region and electrically coupled to a first source/drain region of the first active region;
a bit line contact plug formed in the second active region and electrically coupled to a second source/drain region of the second active region; and
a spacer formed at a sidewall of any of the storage node contact plug and the bit line contact plug so as to electrically insulate the storage node contact plug from the bit line contact plug,
wherein the spacer includes oxide and free of nitride,
wherein the storage node contact plug is formed with at least two conductive materials having different dopant concentration levels,
wherein the storage node contact plug includes:
a lightly doped contact plug disposed in a lower portion of the storage node contact hole; and
a highly doped contact plug disposed in an upper portion of the storage node contact hole and over the lightly doped contact plug.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein the spacer consists essentially of oxide.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, wherein the spacer has a varying thickness according to elevation with respect to the substrate, the spacer having a less thickness proximate the substrate.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8, wherein the storage node contact plug is extends over device isolation region.