# US 8,569,812 B2 · Floating body memory cell having gates favoring different conductivity type regions

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- Number: US 8,569,812 B2
- Document ID: US8569812B2
- Status: Granted
- Kind: B2
- Application number: 13/534,985
- Filed: 2012-06-27
- Published: 2012-10-25
- Granted: 2013-10-29
- Earliest claimed: 2006-12-22
- Assignees: Intel Corporation
- Applicants: Peter L. D. Chang; Uygar E. Avci; David L. Kencke; Ibrahim Ban
- Inventors: Peter L. D. Chang; Uygar E. Avci; David L. Kencke; Ibrahim Ban
- Web page: https://patentgrep.com/patent/US8569812B2

## CPC

- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/01: {Manufacture or treatment}
- H10B 12/36: {the transistor being a FinFET}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/711: {having floating bodies}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10B 12/056: {the transistor being a FinFET}
- Y10S 257/903: FET configuration adapted for use as static memory cell
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

## Claims

### Claim 1

A memory including:
a plurality of first and second, parallel, spaced-apart fins, having alternate first and second regions between the fins defined by side surfaces on adjacent fins facing each other;
first gate structures disposed on alternate first regions of the fins;
second gate structures disposed on alternate second regions of the fins;
wherein the second gate structures have at least one of a different gate oxide thickness and a different gate material than the first gate structures.

### Claim 2 (depends on 1)

The memory of claim 1, wherein the fins include n type source and drain regions, and the oxide thickness of the second gate structure is thicker than the first gate structure.

### Claim 3 (depends on 2)

The memory of claim 2, wherein the gate material of second gate structures is formed from a metal having a work function in the range of approximately 4.6 to 5.2 eV.

### Claim 4 (depends on 3)

The memory of claim 3, wherein the fins are integral with a bulk silicon substrate.