# US 8,569,810 B2 · Metal semiconductor alloy contact with low resistance

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- Number: US 8,569,810 B2
- Document ID: US8569810B2
- Status: Granted
- Kind: B2
- Application number: 12/961,553
- Filed: 2010-12-07
- Published: 2012-06-07
- Granted: 2013-10-29
- Earliest claimed: 2010-12-07
- Assignees: International Business Machines Corporation; Globalfoundries Inc.
- Applicants: Jian Yu; Jeffrey B. Johnson; Zhengwen Li; Chengwen Pei; Michael Hargrove
- Inventors: Jian Yu; Jeffrey B. Johnson; Zhengwen Li; Chengwen Pei; Michael Hargrove
- Web page: https://patentgrep.com/patent/US8569810B2

## CPC

- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

## Claims

### Claim 1

A semiconductor device comprising:
a gate structure on a channel portion of a semiconductor substrate;
a source region and a drain region on opposing sides of the channel portion of the semiconductor substrate;
an interlevel dielectric layer present on the semiconductor substrate, the source region, the drain region and the gate structure;
an opening to at least one of the source region and the drain region present through the interlevel dielectric layer;
at least one dielectric sidewall spacer in direct contact with a sidewall of the opening;
a metal semiconductor alloy contact present at a base portion of the opening and extending into the semiconductor substrate, wherein a portion of the metal semiconductor alloy contact that extends into the semiconductor substrate is present under and in direct contact with a base surface of the at least one dielectric sidewall spacer, wherein sidewalls of the metal semiconductor alloy contact are substantially aligned with the sidewall of the opening; and
an interconnect filling the opening, wherein the interconnect is in contact with the metal semiconductor alloy contact and the at least one dielectric sidewall spacer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the metal semiconductor alloy contact comprises nickel silicide (NiSix), nickel platinum silicide (NiPtySix), cobalt silicide (CoSix), tantalum silicide (TaSix), or titanium silicide (TiSix).

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the interconnect is composed of a metal selected from the group consisting of tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta) and combinations thereof.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure comprises a high-k dielectric layer that is present on the channel portion of the semiconductor substrate, and a metal gate conductor that is present on the high-k dielectric layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the metal semiconductor alloy contact is separated from the gate structure by a dimension ranging from 10 nm to 50 nm.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a portion of the semiconductor substrate that is separating the metal semiconductor alloy contact from the gate structure is composed of single crystal or polycrystalline material.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the metal gate conductor is composed of TiN, TaN, Al, W or a combination thereof.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure has a width ranging from 10 nm to 100 nm.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein an adjacent semiconductor device is present on the semiconductor substrate separated from the semiconductor device by a pitch ranging from 60 nm to 200 nm.