# US 8,569,801 B2 · Three-dimensional CMOS circuit on two offset substrates and method for making same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,569,801 B2
- Document ID: US8569801B2
- Status: Granted
- Kind: B2
- Application number: 13/059,483
- Filed: 2009-08-10
- Published: 2011-06-16
- Granted: 2013-10-29
- Earliest claimed: 2008-08-26
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Applicants: Benjamin Vincent
- Inventors: Benjamin Vincent
- Web page: https://patentgrep.com/patent/US8569801B2

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 62/405: {Orientations of crystalline planes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 88/01: {Manufacture or treatment}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A three-dimensional CMOS circuit having at least a first N-conductivity field-effect transistor and a second P-conductivity field-effect transistor respectively formed on first and second crystalline substrates. The first field-effect transistor is oriented, in the first substrate, with a first secondary crystallographic orientation. The second field-effect transistor is oriented, in the second substrate, with a second secondary crystallographic orientation. The orientations of the first and second transistors form a different angle from the angle formed, in one of the substrates, by the first and second secondary crystallographic directions. The first and second substrates are assembled vertically.

## Claims

### Claim 1

A three-dimensional CMOS circuit including:
a first crystalline substrate;
a second crystalline substrate disposed overlapping the first crystalline substrate;
a first field-effect transistor of a first conductivity type formed on the first crystalline substrate, the first field-effect transistor presenting a first source-drain axis oriented in a first secondary crystallographic direction of the first crystalline substrate;
a second field-effect transistor of a second conductivity type formed on the second crystalline substrate, the second field-effect transistor presenting a second source-drain axis oriented in a second secondary crystallographic direction of the second crystalline substrate,
wherein:
the first source-drain axis and the second source-drain axis form a first angle different from a second angle formed, in the first substrate, by the first secondary crystallographic direction and the second secondary crystallographic direction, and
the first angle is in a ]0, 90[ range.

### Claim 2 (depends on 1)

The circuit according to claim 1, wherein the first angle is smaller angle than the second angle.

### Claim 3 (depends on 1)

The circuit according to claim 1, wherein the first secondary crystallographic direction and the second secondary crystallographic direction are identical.

### Claim 4 (depends on 1)

The circuit according to claim 1, wherein the first secondary crystallographic direction is <110> type.

### Claim 5 (depends on 1)

The circuit according to claim 1, wherein the second secondary crystallographic direction is <100> type.

### Claim 6

A method for three-dimensional co-integration of a CMOS circuit successively comprising:
providing a first crystalline substrate with a first main crystallographic direction, the first crystalline substrate comprising first field-effect transistors, the first field-effect transistor presenting a first source-drain axis oriented in a first secondary crystallographic direction of the first substrate;
providing a second crystalline substrate with a second main crystallographic direction;
covering the first crystalline substrate with the second crystalline substrate, the first field-effect transistors being disposed between the first crystalline substrate and the second crystalline substrate, the first main crystallographic direction and the second main crystallographic direction being offset before covering; and
forming a second field-effect transistor on the second crystalline substrate, the second field-effect transistor presenting a second source-drain axis oriented in a second secondary crystallographic direction of the second crystalline substrate,
wherein an angle between the first source-drain axis and the second source-drain axis is in a ]0, 90[ range.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the first secondary crystallographic direction is of <110> type.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the second secondary crystallographic direction is of <100> type.